init

conf/layer.conf

@@ -0,0 +1,17 @@
+# We have a conf and classes directory, append to BBPATH
+BBPATH .= ":${LAYERDIR}"
+
+# We have a recipes directory, add to BBFILES
+BBFILES += "${LAYERDIR}/recipes*/*/*.bb ${LAYERDIR}/recipes*/*/*.bbappend"
+
+BBFILE_COLLECTIONS += "feur"
+BBFILE_PATTERN_feur := "^${LAYERDIR}/"
+BBFILE_PRIORITY_feur = "10"
+
+# This should only be incremented on significant changes that will
+# cause compatibility issues with other layers
+LAYERVERSION_feur = "1"
+
+LAYERDEPENDS_feur = "core meta-python meta-arm sunxi"
+
+LAYERSERIES_COMPAT_feur = "honister kirkstone langdale mickledore nanbield scarthgap"

recipes-extended/linux/linux-changes.inc

@@ -0,0 +1,6 @@
+
+do_configure:prepend() {
+    if [ -e ${UNPACKDIR}/logo_linux_clut224.ppm ]; then
+    install -m 0644 ${UNPACKDIR}/logo_linux_clut224.ppm drivers/video/logo/logo_linux_clut224.ppm
+    fi
+}

recipes-extended/linux/linux-mainline-changes.inc

@@ -0,0 +1,16 @@
+
+include linux-changes.inc
+
+FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
+
+SRC_URI:append = " \
+	   file://defconfig \
+	   file://sunxi-kmeta;type=kmeta;name=sunxi-kmeta;destsuffix=sunxi-kmeta \
+"
+
+SRC_URI:append:orange-pi-prime = " \
+	file://0001-dts-sun50i-h5-enable-power-button-for-orange-pi-prime.patch \
+	file://0002-dts-sun50i-h5-orange-pi-prime-add-regulator.patch \
+	file://0003-dts-sun50i-h5-orange-pi-prime-add-rtl8723cs.patch \
+"
+

recipes-extended/linux/linux-mainline/orange-pi-prime/0001-dts-sun50i-h5-enable-power-button-for-orange-pi-prime.patch

@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Sat, 15 Jul 2023 17:06:17 +0000
+Subject: arm64: dts: sun50i: h5: enable power button for orangepi prime
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index f430acd8558f..35e09098570f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -63,8 +63,9 @@ gpio-keys {
+ 
+ 		key-sw4 {
+ 			label = "sw4";
+-			linux,code = <BTN_0>;
++			linux,code = <KEY_POWER>;
+ 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
++			wakeup-source;
+ 		};
+ 	};
+ 
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/orange-pi-prime/0002-dts-sun50i-h5-orange-pi-prime-add-regulator.patch

@@ -0,0 +1,66 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 19:34:31 +0300
+Subject: arm64:dts: sun50i-h5-orangepi-prime add regulator
+
+---
+ .../allwinner/sun50i-h5-orangepi-prime.dts    | 30 +++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index 998396bc0..6dc6850c1 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -8,6 +8,7 @@
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/sun4i-a10.h>
+ 
+ / {
+ 	model = "Xunlong Orange Pi Prime";
+@@ -93,6 +94,10 @@ wifi_pwrseq: wifi_pwrseq {
+ 	};
+ };
+ 
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpux>;
++};
++
+ &codec {
+ 	allwinner,audio-routing =
+ 		"Line Out", "LINEOUT",
+@@ -188,6 +193,31 @@ &ohci3 {
+ 	status = "okay";
+ };
+ 
++&r_i2c {
++	status = "okay";
++
++	reg_vdd_cpux: regulator@65 {
++		compatible = "silergy,sy8106a";
++		reg = <0x65>;
++		regulator-name = "vdd-cpux";
++		silergy,fixed-microvolt = <1200000>;
++		/*
++		 * The datasheet uses 1.1V as the minimum value of VDD-CPUX,
++		 * however both the Armbian DVFS table and the official one
++		 * have operating points with voltage under 1.1V, and both
++		 * DVFS table are known to work properly at the lowest
++		 * operating point.
++		 *
++		 * Use 1.0V as the minimum voltage instead.
++		 */
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-ramp-delay = <200>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+-- 
+2.25.1

recipes-extended/linux/linux-mainline/orange-pi-prime/0003-dts-sun50i-h5-orange-pi-prime-add-rtl8723cs.patch

@@ -0,0 +1,35 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 7 Feb 2022 19:11:07 +0300
+Subject: arm64:dts: sun50i-h5-orangepi-prime add rtl8723cs
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index 8b92d5e77220..f430acd8558f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -25,6 +25,7 @@ reg_vcc3v3: vcc3v3 {
+ 	aliases {
+ 		ethernet0 = &emac;
+ 		serial0 = &uart0;
++		ethernet1 = &rtl8723cs;
+ 	};
+ 
+ 	chosen {
+@@ -174,6 +175,10 @@ &mmc1 {
+ 	bus-width = <4>;
+ 	non-removable;
+ 	status = "okay";
++
++	rtl8723cs: sdio_wifi@1 {
++		reg = <1>;
++	};
+ };
+ 
+ &ohci0 {
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/add-nodes-for-sunxi-info-addr-dump-reg.patch

@@ -0,0 +1,72 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sat, 16 Apr 2022 11:51:35 +0300
+Subject: add nodes for sunxi-info, sunxi-addr and sunxi-dump-reg
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 ++++++++++
+ 1 file changed, 19 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 538c90663602..6365cce07304 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -1243,6 +1243,25 @@ ths: thermal-sensor@5070400 {
+ 			nvmem-cell-names = "calibration";
+ 			#thermal-sensor-cells = <1>;
+ 		};
++
++		sunxi-info {
++			compatible = "allwinner,sun50i-h6-sys-info";
++			status = "okay";
++		};
++
++		addr_mgt: addr-mgt {
++			compatible = "allwinner,sunxi-addr_mgt";
++			type_addr_wifi = <0x2>;
++			type_addr_bt = <0x2>;
++			type_addr_eth = <0x2>;
++			status = "okay";
++		};
++
++		dump_reg: dump_reg@20000 {
++			compatible = "allwinner,sunxi-dump-reg";
++			reg = <0x0 0x03001000 0x0 0x0f20>;
++			status = "okay";
++		};
+ 	};
+ 
+ 	thermal-zones {
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 98735d39e6e8..5ff1b357a25b 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -1053,6 +1053,25 @@ ths: thermal-sensor@5070400 {
+ 			nvmem-cell-names = "calibration";
+ 			#thermal-sensor-cells = <1>;
+ 		};
++
++		dump_reg: dump_reg@20000 {
++			compatible = "allwinner,sunxi-dump-reg";
++			reg = <0x0 0x03001000 0x0 0x0f20>;
++			status = "okay";
++		};
++
++		sunxi-info {
++			compatible = "allwinner,sun50i-h616-sys-info";
++			status = "okay";
++		};
++
++		addr_mgt: addr-mgt {
++			compatible = "allwinner,sunxi-addr_mgt";
++			type_addr_wifi = <0x2>;
++			type_addr_bt = <0x2>;
++			type_addr_eth = <0x2>;
++			status = "okay";
++		};
+ 	};
+ 
+ 	thermal-zones {
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/arm64-dts-allwinner-h616-Add-device-node-for-SID.patch

@@ -0,0 +1,41 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Kali Prasad <kprasadvnsi@protonmail.com>
+Date: Sun, 19 Sep 2021 08:02:27 +0000
+Subject: arm64: dts: allwinner: h616: Add device node for SID
+
+The device tree binding for H616's SID controller.
+
+Signed-off-by: Kali Prasad <kprasadvnsi@protonmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 15 ++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 45359b0d317a..7ad1982fb47f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -171,6 +171,21 @@ ccu: clock@3001000 {
+ 			#reset-cells = <1>;
+ 		};
+ 
++		sid: efuse@3006000 {
++			compatible = "allwinner,sun50i-h616-sid";
++			reg = <0x03006000 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			cpu_speed_grade: cpu-speed-grade@0 {
++				reg = <0x00 0x02>;
++			};
++
++			ths_calibration: thermal-sensor-calibration@14 {
++				reg = <0x14 0x8>;
++			};
++		};
++
+ 		watchdog: watchdog@30090a0 {
+ 			compatible = "allwinner,sun50i-h616-wdt",
+ 				     "allwinner,sun6i-a31-wdt";
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-v1_6_2.patch

@@ -0,0 +1,473 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: AGM1968 <AGM1968@users.noreply.github.com>
+Date: Tue, 23 May 2023 16:43:00 +0000
+Subject: arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-v1_6_2
+ arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
+ arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+ drivers/cpufreq/cpufreq-dt-platdev.c drivers/cpufreq/sun50i-cpufreq-nvmem.c
+
+Signed-off-by: AGM1968 <AGM1968@users.noreply.github.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi       | 75 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi      | 64 +++++++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi |  1 +
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts |  5 +
+ arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts | 62 ++-----------
+ drivers/cpufreq/cpufreq-dt-platdev.c                         |  2 +
+ drivers/cpufreq/sun50i-cpufreq-nvmem.c                       | 92 +++++++---
+ 7 files changed, 221 insertions(+), 80 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
+new file mode 100644
+index 000000000000..36f2950367c6
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
+@@ -0,0 +1,75 @@
++//SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++//Testing Version 1  from: AGM1968 <AGM1968@users.noreply.github.com>
++//Noted: PLL_CPUX = 24 MHz*N/P (WIP)
++
++/ {
++	cpu_opp_table: opp-table-cpu {
++		compatible = "allwinner,sun50i-h616-operating-points";
++		nvmem-cells = <&cpu_speed_grade>;
++		opp-shared;
++ 
++		opp-480000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <480000000>;
++			opp-microvolt-speed0 = <820000 820000 1100000>; 
++			opp-microvolt-speed1 = <880000 880000 1100000>;
++			opp-microvolt-speed2 = <880000 880000 1100000>;
++		};
++	
++		opp-600000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <600000000>;
++			opp-microvolt-speed0 = <820000 820000 1100000>;
++			opp-microvolt-speed1 = <880000 880000 1100000>;
++			opp-microvolt-speed2 = <880000 880000 1100000>;
++		};
++
++		opp-792000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <792000000>;
++		        opp-microvolt-speed0 = <860000 860000 1100000>;
++			opp-microvolt-speed1 = <940000 940000 1100000>;
++			opp-microvolt-speed2 = <940000 940000 1100000>;
++		};
++
++		opp-1008000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1008000000>;
++			opp-microvolt-speed0 = <900000 900000 1100000>;
++			opp-microvolt-speed1 = <1020000 1020000 1100000>;
++			opp-microvolt-speed2 = <1020000 1020000 1100000>;
++		};
++
++		opp-1200000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt-speed0 = <960000 960000 1100000>;
++			opp-microvolt-speed1 = <1100000 1100000 1100000>;
++			opp-microvolt-speed2 = <1100000 1100000 1100000>;
++		};
++
++		opp-1512000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1512000000>;
++			opp-microvolt-speed0 = <1100000 1100000 1100000>;
++			opp-microvolt-speed1 = <1100000 1100000 1100000>;
++			opp-microvolt-speed2 = <1100000 1100000 1100000>;
++		};
++	};
++};
++
++&cpu0 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++ 
++&cpu1 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++ 
++&cpu2 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++ 
++&cpu3 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 0666d16ba7d0..54d706286554 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -7,6 +7,7 @@
+  */
+ 
+ #include "sun50i-h616.dtsi"
++#include "sun50i-h616-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+index 8d8009c7f9a3..41a5a4013091 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+@@ -12,6 +12,11 @@ / {
+ 	compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
+ };
+ 
++&cpu0  {
++	cpu-supply = <&reg_dcdca>;
++	status = "okay";
++};
++
+ &emac0 {
+ 	phy-supply = <&reg_dcdce>;
+ };
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+new file mode 100644
+index 0000000000000..0509e3fb22e26
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+@@ -0,0 +1,64 @@
++
++
++&r_i2c {
++	status = "okay";
++
++	axp313: pmic@36 {
++		compatible = "x-powers,axp313a";
++		reg = <0x36>;
++		#interrupt-cells = <1>;
++		interrupt-controller;
++		interrupt-parent = <&pio>;
++		interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>;	/* PC9 */
++
++		vin1-supply = <&reg_vcc5v>;
++		vin2-supply = <&reg_vcc5v>;
++		vin3-supply = <&reg_vcc5v>;
++
++		regulators {
++			/* Supplies VCC-PLL and DRAM */
++			reg_aldo1: aldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc1v8";
++			};
++
++			/* Supplies VCC-IO, so needs to be always on. */
++			reg_dldo1: dldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc3v3";
++			};
++
++			reg_dcdc1: dcdc1 {
++				regulator-always-on;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <990000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-name = "vdd-gpu-sys";
++			};
++
++			reg_dcdc2: dcdc2 {
++				regulator-always-on;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-ramp-delay = <200>;
++				regulator-name = "vdd-cpu";
++			};
++
++			reg_dcdc3: dcdc3 {
++				regulator-always-on;
++				regulator-min-microvolt = <1100000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-name = "vdd-dram";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
+index 00fe28caac93..edbfc83f390a 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
+@@ -6,12 +6,18 @@
+ /dts-v1/;
+ 
+ #include "sun50i-h616-orangepi-zero.dtsi"
++#include "sun50i-h618-cpu-dvfs.dtsi"
+ 
+ / {
+ 	model = "OrangePi Zero3";
+ 	compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
+ };
+ 
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++	status = "okay";
++};
++
+ &emac0 {
+ 	phy-supply = <&reg_dldo1>;
+ };
+@@ -31,62 +37,6 @@ &mmc0 {
+ 	vmmc-supply = <&reg_dldo1>;
+ };
+ 
+-&r_i2c {
+-	status = "okay";
+-
+-	axp313: pmic@36 {
+-		compatible = "x-powers,axp313a";
+-		reg = <0x36>;
+-		#interrupt-cells = <1>;
+-		interrupt-controller;
+-		interrupt-parent = <&pio>;
+-		interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>;	/* PC9 */
+-
+-		vin1-supply = <&reg_vcc5v>;
+-		vin2-supply = <&reg_vcc5v>;
+-		vin3-supply = <&reg_vcc5v>;
+-
+-		regulators {
+-			/* Supplies VCC-PLL, so needs to be always on. */
+-			reg_aldo1: aldo1 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <1800000>;
+-				regulator-max-microvolt = <1800000>;
+-				regulator-name = "vcc1v8";
+-			};
+-
+-			/* Supplies VCC-IO, so needs to be always on. */
+-			reg_dldo1: dldo1 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <3300000>;
+-				regulator-max-microvolt = <3300000>;
+-				regulator-name = "vcc3v3";
+-			};
+-
+-			reg_dcdc1: dcdc1 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <810000>;
+-				regulator-max-microvolt = <990000>;
+-				regulator-name = "vdd-gpu-sys";
+-			};
+-
+-			reg_dcdc2: dcdc2 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <810000>;
+-				regulator-max-microvolt = <1100000>;
+-				regulator-name = "vdd-cpu";
+-			};
+-
+-			reg_dcdc3: dcdc3 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <1100000>;
+-				regulator-max-microvolt = <1100000>;
+-				regulator-name = "vdd-dram";
+-			};
+-		};
+-	};
+-};
+-
+ &pio {
+ 	vcc-pc-supply = <&reg_dldo1>;
+ 	vcc-pf-supply = <&reg_dldo1>;
+diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
+index fb2875ce1fdd..e63d36839769 100644
+--- a/drivers/cpufreq/cpufreq-dt-platdev.c
++++ b/drivers/cpufreq/cpufreq-dt-platdev.c
+@@ -104,6 +104,8 @@ static const struct of_device_id allowlist[] __initconst = {
+  */
+ static const struct of_device_id blocklist[] __initconst = {
+ 	{ .compatible = "allwinner,sun50i-h6", },
++	{ .compatible = "allwinner,sun50i-h616", },
++	{ .compatible = "allwinner,sun50i-h618", },
+ 
+ 	{ .compatible = "apple,arm-platform", },
+ 
+diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+index 6845ab5034ec..5d85bfe475de 100644
+--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
++++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+@@ -6,6 +6,9 @@
+  * provide the OPP framework with required information.
+  *
+  * Copyright (C) 2019 Yangtao Li <tiny.windzz@gmail.com>
++ *
++ * ADD efuse_xlate to extract SoC version so that h6 and h616 can coexist.
++ * Version 1 AGM1968 <AGM1968@users.noreply.github.com>
+  */
+ 
+ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+@@ -20,25 +23,62 @@
+ 
+ #define MAX_NAME_LEN	7
+ 
+-#define NVMEM_MASK	0x7
+-#define NVMEM_SHIFT	5
++#define SUN50I_H616_NVMEM_MASK 0x22
++#define SUN50I_H616_NVMEM_SHIFT 5
++#define SUN50I_H6_NVMEM_MASK 0x7
++#define SUN50I_H6_NVMEM_SHIFT 5
++
++struct sunxi_cpufreq_soc_data {
++	u32 (*efuse_xlate) (void *efuse);
++};
+ 
+ static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
+ 
++static u32 sun50i_h616_efuse_xlate(void *efuse)
++{
++   u32 efuse_value = (*(u32 *)efuse >> SUN50I_H616_NVMEM_SHIFT) &
++             SUN50I_H616_NVMEM_MASK;
++
++   /* Tested as V1 h616 soc. Expected efuse values are 1 - 3,
++      slowest to fastest */
++   if (efuse_value >=1 && efuse_value <= 3)
++       return efuse_value - 1;
++   else
++       return 0;
++};
++
++static u32 sun50i_h6_efuse_xlate(void *efuse)
++{
++   u32 efuse_value = (*(u32 *)efuse >> SUN50I_H6_NVMEM_SHIFT) &
++             SUN50I_H6_NVMEM_MASK;
++
++   /*
++    * We treat unexpected efuse values as if the SoC was from
++    * the slowest bin. Expected efuse values are 1 - 3, slowest
++    * to fastest.
++   */
++   if (efuse_value >= 1 && efuse_value <= 3)
++       return efuse_value - 1;
++   else
++       return 0;
++};
++
++
+ /**
+  * sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
++ * @soc_data: pointer to sunxi_cpufreq_soc_data context
+  * @versions: Set to the value parsed from efuse
+  *
+  * Returns 0 if success.
+  */
+-static int sun50i_cpufreq_get_efuse(u32 *versions)
++static int sun50i_cpufreq_get_efuse(const struct sunxi_cpufreq_soc_data *soc_data,
++		u32 *versions)
+ {
+ 	struct nvmem_cell *speedbin_nvmem;
+ 	struct device_node *np;
+ 	struct device *cpu_dev;
+-	u32 *speedbin, efuse_value;
++	u32 *speedbin;
+ 	size_t len;
+-	int ret;
+ 
+ 	cpu_dev = get_cpu_device(0);
+ 	if (!cpu_dev)
+@@ -47,10 +87,9 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
+ 	np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
+ 	if (!np)
+ 		return -ENOENT;
+-
+-	ret = of_device_is_compatible(np,
+-				      "allwinner,sun50i-h6-operating-points");
+-	if (!ret) {
++	if (of_device_is_compatible(np, "allwinner,sun50i-h6-operating-points")) {}
++	else if (of_device_is_compatible(np, "allwinner,sun50i-h616-operating-points")) {}
++	else {
+ 		of_node_put(np);
+ 		return -ENOENT;
+ 	}
+@@ -66,17 +105,7 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
+ 	if (IS_ERR(speedbin))
+ 		return PTR_ERR(speedbin);
+ 
+-	efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
+-
+-	/*
+-	 * We treat unexpected efuse values as if the SoC was from
+-	 * the slowest bin. Expected efuse values are 1-3, slowest
+-	 * to fastest.
+-	 */
+-	if (efuse_value >= 1 && efuse_value <= 3)
+-		*versions = efuse_value - 1;
+-	else
+-		*versions = 0;
++	*versions = soc_data->efuse_xlate(speedbin);
+ 
+ 	kfree(speedbin);
+ 	return 0;
+@@ -84,18 +113,23 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
+ 
+ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
+ {
++	const struct of_device_id *match;
+ 	int *opp_tokens;
+ 	char name[MAX_NAME_LEN];
+ 	unsigned int cpu;
+ 	u32 speed = 0;
+ 	int ret;
+ 
++	match = dev_get_platdata(&pdev->dev);
++	if (!match)
++		return -EINVAL;
++
+ 	opp_tokens = kcalloc(num_possible_cpus(), sizeof(*opp_tokens),
+ 			     GFP_KERNEL);
+ 	if (!opp_tokens)
+ 		return -ENOMEM;
+ 
+-	ret = sun50i_cpufreq_get_efuse(&speed);
++	ret = sun50i_cpufreq_get_efuse(match-> data, &speed);
+ 	if (ret) {
+ 		kfree(opp_tokens);
+ 		return ret;
+@@ -159,8 +193,18 @@ static struct platform_driver sun50i_cpufreq_driver = {
+ 	},
+ };
+ 
++static const struct sunxi_cpufreq_soc_data sun50i_h616_data = {
++    .efuse_xlate = sun50i_h616_efuse_xlate,
++};
++
++static const struct sunxi_cpufreq_soc_data sun50i_h6_data = {
++    .efuse_xlate = sun50i_h6_efuse_xlate,
++};
++
+ static const struct of_device_id sun50i_cpufreq_match_list[] = {
+-	{ .compatible = "allwinner,sun50i-h6" },
++	{ .compatible = "allwinner,sun50i-h6", .data = &sun50i_h6_data },
++        { .compatible = "allwinner,sun50i-h616", .data = &sun50i_h616_data },
++        { .compatible = "allwinner,sun50i-h618", .data = &sun50i_h616_data },
+ 	{}
+ };
+ MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list);
+@@ -196,8 +239,8 @@ static int __init sun50i_cpufreq_init(void)
+ 		return ret;
+ 
+ 	sun50i_cpufreq_pdev =
+-		platform_device_register_simple("sun50i-cpufreq-nvmem",
+-						-1, NULL, 0);
++		platform_device_register_data(NULL,
++		"sun50i-cpufreq-nvmem", -1, match, sizeof(*match));
+ 	ret = PTR_ERR_OR_ZERO(sun50i_cpufreq_pdev);
+ 	if (ret == 0)
+ 		return 0;
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/arm64-dts-allwinner-h616-Add-thermal-sensor-and-thermal-zones.patch

@@ -0,0 +1,135 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Kali Prasad <kprasadvnsi@protonmail.com>
+Date: Sun, 19 Sep 2021 08:02:27 +0000
+Subject: arm64: dts: allwinner: h616: Add thermal sensor and thermal zones
+
+There are four sensors, CPU, GPU, VE, and DDR.
+
+Signed-off-by: Kali Prasad <kprasadvnsi@protonmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 75 ++++++++++
+ 1 file changed, 75 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 7ad1982fb47f..8628a9e3dfca 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -9,6 +9,7 @@
+ #include <dt-bindings/clock/sun6i-rtc.h>
+ #include <dt-bindings/reset/sun50i-h616-ccu.h>
+ #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
++#include <dt-bindings/thermal/thermal.h>
+ 
+ / {
+ 	interrupt-parent = <&gic>;
+@@ -25,6 +26,8 @@ cpu0: cpu@0 {
+ 			reg = <0>;
+ 			enable-method = "psci";
+ 			clocks = <&ccu CLK_CPUX>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		cpu1: cpu@1 {
+@@ -33,6 +36,8 @@ cpu1: cpu@1 {
+ 			reg = <1>;
+ 			enable-method = "psci";
+ 			clocks = <&ccu CLK_CPUX>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		cpu2: cpu@2 {
+@@ -41,6 +46,8 @@ cpu2: cpu@2 {
+ 			reg = <2>;
+ 			enable-method = "psci";
+ 			clocks = <&ccu CLK_CPUX>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		cpu3: cpu@3 {
+@@ -49,6 +56,8 @@ cpu3: cpu@3 {
+ 			reg = <3>;
+ 			enable-method = "psci";
+ 			clocks = <&ccu CLK_CPUX>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			#cooling-cells = <2>;
+ 		};
+ 	};
+ 
+@@ -833,5 +842,71 @@ r_rsb: rsb@7083000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 		};
++
++		ths: thermal-sensor@5070400 {
++			compatible = "allwinner,sun50i-h616-ths";
++			reg = <0x05070400 0x400>;
++			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_THS>;
++			clock-names = "bus";
++			resets = <&ccu RST_BUS_THS>;
++			nvmem-cells = <&ths_calibration>;
++			nvmem-cell-names = "calibration";
++			#thermal-sensor-cells = <1>;
++		};
++	};
++
++	thermal-zones {
++		cpu-thermal {
++			polling-delay-passive = <500>;
++			polling-delay = <1000>;
++			thermal-sensors = <&ths 2>;
++			sustainable-power = <1000>;
++			k_po = <20>;
++			k_pu = <40>;
++			k_i = <0>;
++
++			trips {
++				cpu_threshold: trip-point@0 {
++					temperature = <60000>;
++					type = "passive";
++					hysteresis = <0>;
++				};
++				cpu_target: trip-point@1 {
++					temperature = <70000>;
++					type = "passive";
++					hysteresis = <0>;
++				};
++			};
++
++			cooling-maps {
++				map0 {
++					trip = <&cpu_target>;
++					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				};
++			};
++		};
++
++		gpu-thermal {
++			polling-delay-passive = <500>;
++			polling-delay = <1000>;
++			thermal-sensors = <&ths 0>;
++			sustainable-power = <1100>;
++		};
++
++		ve-thermal {
++			polling-delay-passive = <0>;
++			polling-delay = <0>;
++			thermal-sensors = <&ths 1>;
++		};
++
++		ddr-thermal {
++			polling-delay-passive = <0>;
++			polling-delay = <0>;
++			thermal-sensors = <&ths 3>;
++		};
+ 	};
+ };
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/arm64-dts-allwinner-h616-Fix-thermal-zones-missing-trips.patch

@@ -0,0 +1,73 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Micha=C5=82=20Dzieko=C5=84ski?=
+ <michal.dziekonski+github@gmail.com>
+Date: Wed, 3 May 2023 12:17:28 +0000
+Subject: arm64: dts: allwinner: h616: Fix thermal zones (add missing trips)
+
+Signed-off-by: Michal Dziekonski <michal.dziekonski+github@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 29 ++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 8628a9e3dfca..17b13d3193cc 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -877,6 +877,11 @@ cpu_target: trip-point@1 {
+ 					type = "passive";
+ 					hysteresis = <0>;
+ 				};
++				cpu_temp_critical: trip-point@2 {
++					temperature = <110000>;
++					type = "critical";
++					hysteresis = <0>;
++				};
+ 			};
+ 
+ 			cooling-maps {
+@@ -895,18 +900,42 @@ gpu-thermal {
+ 			polling-delay = <1000>;
+ 			thermal-sensors = <&ths 0>;
+ 			sustainable-power = <1100>;
++
++			trips {
++				gpu_temp_critical: trip-point@0 {
++					temperature = <110000>;
++					type = "critical";
++					hysteresis = <0>;
++				};
++			};
+ 		};
+ 
+ 		ve-thermal {
+ 			polling-delay-passive = <0>;
+ 			polling-delay = <0>;
+ 			thermal-sensors = <&ths 1>;
++
++			trips {
++				ve_temp_critical: trip-point@0 {
++					temperature = <110000>;
++					type = "critical";
++					hysteresis = <0>;
++				};
++			};
+ 		};
+ 
+ 		ddr-thermal {
+ 			polling-delay-passive = <0>;
+ 			polling-delay = <0>;
+ 			thermal-sensors = <&ths 3>;
++
++			trips {
++				ddr_temp_critical: trip-point@0 {
++					temperature = <110000>;
++					type = "critical";
++					hysteresis = <0>;
++				};
++			};
+ 		};
+ 	};
+ };
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/arm64-dts-allwinner-h616-LED-green_power_on-red_status_heartbeat.patch

@@ -0,0 +1,39 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: AGM1968 <AGM1968@users.noreply.github.com>
+Date: Wed, 31 May 2023 08:12:00 +0000
+Subject: LED-green_power_on-red_status_heartbeat
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+
+Signed-off-by: AGM1968 <AGM1968@users.noreply.github.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 0666d16ba7d0..19451a0c85ae 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -26,16 +26,17 @@ leds {
+ 		compatible = "gpio-leds";
+ 
+ 		led-0 {
+-			function = LED_FUNCTION_POWER;
++			function = LED_FUNCTION_STATUS;
+ 			color = <LED_COLOR_ID_RED>;
+ 			gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+-			default-state = "on";
++			linux,default-trigger = "heartbeat";
+ 		};
+ 
+ 		led-1 {
+-			function = LED_FUNCTION_STATUS;
++			function = LED_FUNCTION_POWER;
+ 			color = <LED_COLOR_ID_GREEN>;
+ 			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
++			default-state = "on";
+ 		};
+ 	};
+ 
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch

@@ -0,0 +1,38 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Fri, 15 Oct 2021 21:07:46 +0200
+Subject: arm64:dts: allwinner: sun50i-h616 Add GPU node
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 14 ++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 44f8ae11ca16..26ef79c5d895 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -108,6 +108,20 @@ soc {
+ 		#size-cells = <1>;
+ 		ranges = <0x0 0x0 0x0 0x40000000>;
+ 
++		gpu: gpu@1800000 {
++			compatible = "allwinner,sun50i-h616-mali",
++				     "arm,mali-bifrost";
++			reg = <0x1800000 0x40000>;
++			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "job", "mmu", "gpu";
++			clocks = <&ccu CLK_GPU0>, <&ccu CLK_BUS_GPU>;
++			clock-names = "core", "bus";
++			resets = <&ccu RST_BUS_GPU>;
++			status = "disabled";
++		};
++
+ 		syscon: syscon@3000000 {
+ 			compatible = "allwinner,sun50i-h616-system-control";
+ 			reg = <0x03000000 0x1000>;
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch

@@ -0,0 +1,55 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Fri, 15 Oct 2021 21:14:55 +0200
+Subject: arm64:dts:allwinner: sun50i-h616 Add VPU node
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 24 ++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 26ef79c5d895..944ff2747d27 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -122,6 +122,17 @@ gpu: gpu@1800000 {
+ 			status = "disabled";
+ 		};
+ 
++		video-codec@1c0e000 {
++			compatible = "allwinner,sun50i-h616-video-engine";
++			reg = <0x01c0e000 0x2000>;
++			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
++				 <&ccu CLK_MBUS_VE>;
++			clock-names = "ahb", "mod", "ram";
++			resets = <&ccu RST_BUS_VE>;
++			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
++			allwinner,sram = <&ve_sram 1>;
++		};
++
+ 		syscon: syscon@3000000 {
+ 			compatible = "allwinner,sun50i-h616-system-control";
+ 			reg = <0x03000000 0x1000>;
+@@ -136,6 +147,19 @@ sram_c: sram@28000 {
+ 				#size-cells = <1>;
+ 				ranges = <0 0x00028000 0x30000>;
+ 			};
++
++			sram_c1: sram@1a00000 {
++				compatible = "mmio-sram";
++				reg = <0x01a00000 0x200000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x01a00000 0x200000>;
++
++				ve_sram: sram-section@0 {
++					compatible = "allwinner,sun50i-h616-sram-c1";
++					reg = <0x000000 0x200000>;
++				};
++			};
+ 		};
+ 
+ 		ccu: clock@3001000 {
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/arm64-dts-allwinner-sun50i-h616-PG-12c-pins.patch

@@ -0,0 +1,39 @@
+From a3e54a502cf754b148a8ad06580a3c256bc42b09 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@xxxxx.com>
+Date: Thu, 22 Feb 2024 19:31:11 -0500
+Subject: [PATCH] arch: arm64: dts: allwinner: sun50i-h616: PG 12c pins
+
+pins = "PG17", "PG18";
+pins = "PG15", "PG16";
+
+Signed-off-by: Patrick Yavitz <pyavitz@xxxxx.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 17df57e2db0a..e5ce4214a43b 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -334,6 +334,18 @@ i2c4_ph_pins: i2c4-ph-pins {
+ 				function = "i2c4";
+ 			};
+ 
++			/omit-if-no-ref/
++			i2c3_pg_pins: i2c3-pg-pins {
++				pins = "PG17", "PG18";
++				function = "i2c3";
++			};
++
++			/omit-if-no-ref/
++			i2c4_pg_pins: i2c4-pg-pins {
++				pins = "PG15", "PG16";
++				function = "i2c4";
++			};
++
+ 			ir_rx_pin: ir-rx-pin {
+ 				pins = "PH10";
+ 				function = "ir_rx";
+-- 
+2.39.2
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/arm64-dts-allwinner-sun50i-h616-spi1-cs1-pin.patch

@@ -0,0 +1,30 @@
+From 64b0221e526f6359a39ab3beb9a693dc964b1112 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@xxxxx.com>
+Date: Wed, 6 Mar 2024 06:51:01 -0500
+Subject: [PATCH] arch: arm64: dts: allwinner: sun50i-h616: spi1 cs1 pin
+
+Signed-off-by: Patrick Yavitz <pyavitz@xxxxx.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 33f8c758b9e6..1354dca01e78 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -397,6 +397,12 @@ spi1_cs0_pin: spi1-cs0-pin {
+ 				function = "spi1";
+ 			};
+ 
++			/omit-if-no-ref/
++			spi1_cs1_pin: spi1-cs1-pin {
++				pins = "PH9";
++				function = "spi1";
++			};
++
+ 			uart0_ph_pins: uart0-ph-pins {
+ 				pins = "PH0", "PH1";
+ 				function = "uart0";
+-- 
+2.39.2
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2.patch

@@ -0,0 +1,69 @@
+From 8e36084386d07a07f755bda978875b1354162019 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Wed, 13 Dec 2023 19:15:45 +0000
+Subject: [PATCH] arm64: dts: h616: add wifi support for orange pi zero 2 and
+ zero3
+
+---
+ .../allwinner/sun50i-h616-orangepi-zero.dtsi  | 38 +++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 19451a0c85ae..400966667d1e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -59,6 +59,34 @@ reg_usb1_vbus: regulator-usb1-vbus {
+ 		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ 		status = "okay";
+ 	};
++
++	reg_vcc33_wifi: vcc33-wifi {
++		/* Always on 3.3V regulator for WiFi and BT */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc33-wifi";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc5v>;
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc33_wifi>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "osc32k-out";
++		reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
++		post-power-on-delay-ms = <200>;
++	};
+ };
+ 
+ &ehci1 {
+@@ -90,6 +118,16 @@ &mmc0 {
+ 	status = "okay";
+ };
+ 
++&mmc1 {
++	vmmc-supply = <&reg_vcc33_wifi>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	mmc-ddr-1_8v;
++	status = "okay";
++};
++
+ &ohci1 {
+ 	status = "okay";
+ };
+-- 
+2.34.1
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/arm64-dts-sun50i-h616-Add-dma-node.patch

@@ -0,0 +1,53 @@
+From 8cdd9309fce75995cf3068be5c7ffb65cec51cff Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Wed, 3 Jan 2024 09:53:55 +0000
+Subject: [PATCH] arm64: dts: sun50i-h616: Add dma node
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 2424a2827455..e71b79ebced8 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -170,6 +170,18 @@ mixer0_out_tcon_top_mixer0: endpoint {
+ 			};
+ 		};
+ 
++		dma: dma-controller@3002000 {
++			compatible = "allwinner,sun50i-h6-dma";
++			reg = <0x03002000 0x1000>;
++			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
++			clock-names = "bus", "mbus";
++			dma-channels = <16>;
++			dma-requests = <49>;
++			resets = <&ccu RST_BUS_DMA>;
++			#dma-cells = <1>;
++		};
++
+ 		gpu: gpu@1800000 {
+ 			compatible = "allwinner,sun50i-h616-mali",
+ 				     "arm,mali-bifrost";
+@@ -606,6 +618,8 @@ spi0: spi@5010000 {
+ 			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ 			clock-names = "ahb", "mod";
++			dmas = <&dma 22>, <&dma 22>;
++			dma-names = "rx", "tx";
+ 			resets = <&ccu RST_BUS_SPI0>;
+ 			pinctrl-names = "default";
+ 			pinctrl-0 = <&spi0_pins>;
+@@ -621,6 +635,8 @@ spi1: spi@5011000 {
+ 			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ 			clock-names = "ahb", "mod";
++			dmas = <&dma 23>, <&dma 23>;
++			dma-names = "rx", "tx";
+ 			resets = <&ccu RST_BUS_SPI1>;
+ 			pinctrl-names = "default";
+ 			pinctrl-0 = <&spi1_pins>;
+-- 
+2.34.1
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch

@@ -0,0 +1,29 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Fri, 15 Oct 2021 21:09:42 +0200
+Subject: arm64:dts: sun50i-h616-orangepi-zero2 Enable GPU mali
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+index d83852e72f06..8d8009c7f9a3 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+@@ -16,6 +16,11 @@ &emac0 {
+ 	phy-supply = <&reg_dcdce>;
+ };
+ 
++&gpu {
++	mali-supply = <&reg_dcdcc>;
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_dcdce>;
+ };
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch

@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 14 Dec 2022 20:15:41 +0300
+Subject: arm64: dts: sun50i-h616-orangepi-zero2: reg_usb1_vbus status ok
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 15290e6892fc..0666d16ba7d0 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -56,6 +56,7 @@ reg_usb1_vbus: regulator-usb1-vbus {
+ 		vin-supply = <&reg_vcc5v>;
+ 		enable-active-high;
+ 		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
++		status = "okay";
+ 	};
+ };
+ 
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch

@@ -0,0 +1,41 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Kali Prasad <kprasadvnsi@protonmail.com>
+Date: Sun, 19 Sep 2021 08:02:27 +0000
+Subject: drv:nvmem:sunxi_sid: Support SID on H616
+
+Add support for H616's SID controller. It supports 4K-bit
+EFUSE.
+
+Signed-off-by: Kali Prasad <kprasadvnsi@protonmail.com>
+---
+ drivers/nvmem/sunxi_sid.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
+index 5d364d85347f..c526fe4abe22 100644
+--- a/drivers/nvmem/sunxi_sid.c
++++ b/drivers/nvmem/sunxi_sid.c
+@@ -204,6 +204,12 @@ static const struct sunxi_sid_cfg sun50i_h6_cfg = {
+ 	.size = 0x200,
+ };
+ 
++static const struct sunxi_sid_cfg sun50i_h616_cfg = {
++	.value_offset = 0x200,
++	.size = 0x100,
++	.need_register_readout = true,
++};
++
+ static const struct of_device_id sunxi_sid_of_match[] = {
+ 	{ .compatible = "allwinner,sun4i-a10-sid", .data = &sun4i_a10_cfg },
+ 	{ .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg },
+@@ -213,6 +219,7 @@ static const struct of_device_id sunxi_sid_of_match[] = {
+ 	{ .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg },
+ 	{ .compatible = "allwinner,sun50i-h5-sid", .data = &sun50i_a64_cfg },
+ 	{ .compatible = "allwinner,sun50i-h6-sid", .data = &sun50i_h6_cfg },
++	{ .compatible = "allwinner,sun50i-h616-sid", .data = &sun50i_h616_cfg },
+ 	{/* sentinel */},
+ };
+ MODULE_DEVICE_TABLE(of, sunxi_sid_of_match);
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/drv-rtc-sun6i-Add-Allwinner-H616-support.patch

@@ -0,0 +1,45 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Wed, 21 Apr 2021 12:46:43 +0100
+Subject: drv:rtc: sun6i: Add Allwinner H616 support
+
+The H616 RTC changes its day storage to the newly introduced linear day
+scheme, so pair the new compatible string with this feature flag.
+The clock part is missing an external 32768 Hz oscillator input pin,
+for future expansion we must thus ignore any provided clock for now.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/rtc/rtc-sun6i.c | 16 ++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
+index 190ea007d82e..e0b85a0d5645 100644
+--- a/drivers/rtc/rtc-sun6i.c
++++ b/drivers/rtc/rtc-sun6i.c
+@@ -389,6 +389,22 @@ static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
+ CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
+ 		      sun50i_h6_rtc_clk_init);
+ 
++static const struct sun6i_rtc_clk_data sun50i_h616_rtc_data = {
++	.rc_osc_rate = 16000000,
++	.fixed_prescaler = 32,
++	.has_prescaler = 1,
++	.has_out_clk = 1,
++	.no_ext_losc = 1,
++};
++
++static void __init sun50i_h616_rtc_clk_init(struct device_node *node)
++{
++	sun6i_rtc_clk_init(node, &sun50i_h616_rtc_data);
++}
++
++CLK_OF_DECLARE_DRIVER(sun50i_h616_rtc_clk, "allwinner,sun50i-h616-rtc",
++		      sun50i_h616_rtc_clk_init);
++
+ /*
+  * The R40 user manual is self-conflicting on whether the prescaler is
+  * fixed or configurable. The clock diagram shows it as fixed, but there
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch

@@ -0,0 +1,68 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 14 Jun 2021 23:02:45 +0100
+Subject: drv:rtc:sun6i: support RTCs without external LOSCs
+
+Some newer Allwinner RTCs (for instance the one in the H616 SoC) lack
+a pin for an external 32768 Hz oscillator. As a consequence, this LOSC
+can't be selected as the RTC clock source, and we must rely on the
+internal RC oscillator.
+To allow additions of clocks to the RTC node, add a feature bit to ignore
+any provided clocks for now (the current code would think this is the
+external LOSC). Later DTs and code can then for instance add the PLL
+based clock input, and older kernel won't get confused.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/rtc/rtc-sun6i.c | 16 +++++++---
+ 1 file changed, 11 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
+index 02129ea346c1..190ea007d82e 100644
+--- a/drivers/rtc/rtc-sun6i.c
++++ b/drivers/rtc/rtc-sun6i.c
+@@ -137,6 +137,7 @@ struct sun6i_rtc_clk_data {
+ 	unsigned int has_out_clk : 1;
+ 	unsigned int has_losc_en : 1;
+ 	unsigned int has_auto_swt : 1;
++	unsigned int no_ext_losc : 1;
+ };
+ 
+ #define RTC_LINEAR_DAY	BIT(0)
+@@ -260,7 +261,7 @@ static void __init sun6i_rtc_clk_init(struct device_node *node,
+ 	}
+ 
+ 	/* Switch to the external, more precise, oscillator, if present */
+-	if (of_property_present(node, "clocks")) {
++	if (!rtc->data->no_ext_losc && of_get_property(node, "clocks", NULL)) {
+ 		reg |= SUN6I_LOSC_CTRL_EXT_OSC;
+ 		if (rtc->data->has_losc_en)
+ 			reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
+@@ -284,14 +285,19 @@ static void __init sun6i_rtc_clk_init(struct device_node *node,
+ 	}
+ 
+ 	parents[0] = clk_hw_get_name(rtc->int_osc);
+-	/* If there is no external oscillator, this will be NULL and ... */
+-	parents[1] = of_clk_get_parent_name(node, 0);
++	if (rtc->data->no_ext_losc) {
++		parents[1] = NULL;
++		init.num_parents = 1;
++	} else {
++		/* If there is no external oscillator, this will be NULL and */
++		parents[1] = of_clk_get_parent_name(node, 0);
++		/* ... number of clock parents will be 1. */
++		init.num_parents = of_clk_get_parent_count(node) + 1;
++	}
+ 
+ 	rtc->hw.init = &init;
+ 
+ 	init.parent_names = parents;
+-	/* ... number of clock parents will be 1. */
+-	init.num_parents = of_clk_get_parent_count(node) + 1;
+ 	of_property_read_string_index(node, "clock-output-names", 0,
+ 				      &init.name);
+ 
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch

@@ -0,0 +1,41 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sat, 16 Oct 2021 21:26:41 +0200
+Subject: drv:soc: sunxi: sram: Add SRAM C1 H616 handling
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/soc/sunxi/sunxi_sram.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
+index 4458b2e0562b..9e65d8dfe355 100644
+--- a/drivers/soc/sunxi/sunxi_sram.c
++++ b/drivers/soc/sunxi/sunxi_sram.c
+@@ -70,6 +70,12 @@ static struct sunxi_sram_desc sun4i_a10_sram_c1 = {
+ 				  SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")),
+ };
+ 
++static struct sunxi_sram_desc sun50i_h616_sram_c1 = {
++	.data	= SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31,
++				  SUNXI_SRAM_MAP(0x7fffffff, 0, "cpu"),
++				  SUNXI_SRAM_MAP(0, 1, "ve")),
++};
++
+ static struct sunxi_sram_desc sun4i_a10_sram_d = {
+ 	.data	= SUNXI_SRAM_DATA("D", 0x4, 0x0, 1,
+ 				  SUNXI_SRAM_MAP(0, 0, "cpu"),
+@@ -99,6 +105,10 @@ static const struct of_device_id sunxi_sram_dt_ids[] = {
+ 		.compatible	= "allwinner,sun50i-a64-sram-c",
+ 		.data		= &sun50i_a64_sram_c.data,
+ 	},
++	{
++		.compatible	= "allwinner,sun50i-h616-sram-c1",
++		.data		= &sun50i_h616_sram_c1.data,
++	},
+ 	{}
+ };
+ 
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/drv-staging-media-sunxi-cedrus-add-H616-variant.patch

@@ -0,0 +1,44 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Fri, 15 Oct 2021 21:49:45 +0200
+Subject: drv:staging:media:sunxi:cedrus: add H616 variant
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus.c | 13 ++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
+index a0f9f4a5b03a..160bd376eb58 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
+@@ -651,6 +651,15 @@ static const struct cedrus_variant sun50i_h6_cedrus_variant = {
+ 	.mod_rate	= 600000000,
+ };
+ 
++static const struct cedrus_variant sun50i_h616_cedrus_variant = {
++	.capabilities	= CEDRUS_CAPABILITY_UNTILED |
++			  CEDRUS_CAPABILITY_MPEG2_DEC |
++			  CEDRUS_CAPABILITY_H264_DEC |
++			  CEDRUS_CAPABILITY_H265_DEC |
++			  CEDRUS_CAPABILITY_VP8_DEC,
++	.mod_rate	= 600000000,
++};
++
+ static const struct of_device_id cedrus_dt_match[] = {
+ 	{
+ 		.compatible = "allwinner,sun4i-a10-video-engine",
+@@ -696,6 +705,10 @@ static const struct of_device_id cedrus_dt_match[] = {
+ 		.compatible = "allwinner,sun50i-h6-video-engine",
+ 		.data = &sun50i_h6_cedrus_variant,
+ 	},
++	{
++		.compatible = "allwinner,sun50i-h616-video-engine",
++		.data = &sun50i_h6_cedrus_variant,
++	},
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, cedrus_dt_match);
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/h61x-common-6_6.scc

@@ -0,0 +1,24 @@
+# Common patches for h616 and h618
+# Ported from armbian
+# https://github.com/armbian/build/tree/main/patch/kernel/archive/sunxi-6.6/patches.armbian
+# Armabian includes a hack hdmi output not included here: drivers-hack-for-h616-hdmi-video-output.patch
+
+patch add-nodes-for-sunxi-info-addr-dump-reg.patch
+patch arm64-dts-allwinner-h616-Add-device-node-for-SID.patch
+patch arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-v1_6_2.patch
+patch arm64-dts-allwinner-h616-Add-thermal-sensor-and-thermal-zones.patch
+patch arm64-dts-allwinner-h616-Fix-thermal-zones-missing-trips.patch
+patch arm64-dts-allwinner-h616-LED-green_power_on-red_status_heartbeat.patch
+patch arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch
+patch arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch
+patch arm64-dts-allwinner-sun50i-h616-PG-12c-pins.patch
+patch arm64-dts-allwinner-sun50i-h616-spi1-cs1-pin.patch
+
+patch arm64-dts-sun50i-h616-Add-dma-node.patch
+patch drv-nvmem-sunxi_sid-Support-SID-on-H616.patch
+patch drv-rtc-sun6i-Add-Allwinner-H616-support.patch
+patch drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch
+patch drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch
+patch drv-staging-media-sunxi-cedrus-add-H616-variant.patch
+patch nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch

@@ -0,0 +1,58 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sat, 16 Apr 2022 11:19:05 +0300
+Subject: nvmem: sunxi_sid: add sunxi_get_soc_chipid, sunxi_get_serial
+
+---
+ drivers/nvmem/sunxi_sid.c | 28 ++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
+index c526fe4abe22..e522bd1e5edd 100644
+--- a/drivers/nvmem/sunxi_sid.c
++++ b/drivers/nvmem/sunxi_sid.c
+@@ -36,6 +36,25 @@ struct sunxi_sid {
+ 	u32			value_offset;
+ };
+ 
++static unsigned int sunxi_soc_chipid[4];
++static unsigned int sunxi_serial[4];
++
++int sunxi_get_soc_chipid(unsigned char *chipid)
++{
++	memcpy(chipid, sunxi_soc_chipid, 16);
++
++	return 0;
++}
++EXPORT_SYMBOL(sunxi_get_soc_chipid);
++
++int sunxi_get_serial(unsigned       char *serial)
++{
++	memcpy(serial, sunxi_serial, 16);
++
++	return 0;
++}
++EXPORT_SYMBOL(sunxi_get_serial);
++
+ static int sunxi_sid_read(void *context, unsigned int offset,
+ 			  void *val, size_t bytes)
+ {
+@@ -177,6 +196,15 @@ static int sunxi_sid_probe(struct platform_device *pdev)
+ 
+ 	platform_set_drvdata(pdev, nvmem);
+ 
++	nvmem_cfg->reg_read(sid, 0, &sunxi_soc_chipid[0], sizeof(int));
++	nvmem_cfg->reg_read(sid, 4, &sunxi_soc_chipid[1], sizeof(int));
++	nvmem_cfg->reg_read(sid, 8, &sunxi_soc_chipid[2], sizeof(int));
++	nvmem_cfg->reg_read(sid, 12, &sunxi_soc_chipid[3], sizeof(int));
++
++	sunxi_serial[0] = sunxi_soc_chipid[3];
++	sunxi_serial[1] = sunxi_soc_chipid[2];
++	sunxi_serial[2] = (sunxi_soc_chipid[1] >> 16) & 0x0ffff;
++
+ 	return 0;
+ }
+ 
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/h61x/orangepi-zero2-6_6.scc

@@ -0,0 +1,7 @@
+# Kmeta for OPI Zero 2
+include h61x-common-6_6.scc
+
+patch arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2.patch
+patch arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch
+patch arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/ASoC-hdmi-codec-fix-channel-allocation.patch

@@ -0,0 +1,142 @@
+From 91b69779e0875e58d8973b2938a1cc4b7a1c455b Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 25 Mar 2018 22:17:06 +0200
+Subject: [PATCH 22/44] ASoC: hdmi-codec: fix channel allocation
+
+---
+ sound/soc/codecs/hdmi-codec.c | 113 ++++++++++++++++------------------
+ 1 file changed, 52 insertions(+), 61 deletions(-)
+
+--- a/sound/soc/codecs/hdmi-codec.c
++++ b/sound/soc/codecs/hdmi-codec.c
+@@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem h
+  */
+ static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = {
+ 	{ .ca_id = 0x00, .n_ch = 2,
+-	  .mask = FL | FR},
+-	/* 2.1 */
+-	{ .ca_id = 0x01, .n_ch = 4,
+-	  .mask = FL | FR | LFE},
+-	/* Dolby Surround */
++	  .mask = FL | FR },
++	{ .ca_id = 0x03, .n_ch = 4,
++	  .mask = FL | FR | LFE | FC },
+ 	{ .ca_id = 0x02, .n_ch = 4,
+ 	  .mask = FL | FR | FC },
+-	/* surround51 */
++	{ .ca_id = 0x01, .n_ch = 4,
++	  .mask = FL | FR | LFE },
+ 	{ .ca_id = 0x0b, .n_ch = 6,
+-	  .mask = FL | FR | LFE | FC | RL | RR},
+-	/* surround40 */
+-	{ .ca_id = 0x08, .n_ch = 6,
+-	  .mask = FL | FR | RL | RR },
+-	/* surround41 */
+-	{ .ca_id = 0x09, .n_ch = 6,
+-	  .mask = FL | FR | LFE | RL | RR },
+-	/* surround50 */
++	  .mask = FL | FR | LFE | FC | RL | RR },
+ 	{ .ca_id = 0x0a, .n_ch = 6,
+ 	  .mask = FL | FR | FC | RL | RR },
+-	/* 6.1 */
+-	{ .ca_id = 0x0f, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | RL | RR | RC },
+-	/* surround71 */
++	{ .ca_id = 0x09, .n_ch = 6,
++	  .mask = FL | FR | LFE | RL | RR },
++	{ .ca_id = 0x08, .n_ch = 6,
++	  .mask = FL | FR | RL | RR },
++	{ .ca_id = 0x07, .n_ch = 6,
++	  .mask = FL | FR | LFE | FC | RC },
++	{ .ca_id = 0x06, .n_ch = 6,
++	  .mask = FL | FR | FC | RC },
++	{ .ca_id = 0x05, .n_ch = 6,
++	  .mask = FL | FR | LFE | RC },
++	{ .ca_id = 0x04, .n_ch = 6,
++	  .mask = FL | FR | RC },
+ 	{ .ca_id = 0x13, .n_ch = 8,
+ 	  .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC },
+-	/* others */
+-	{ .ca_id = 0x03, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC },
+-	{ .ca_id = 0x04, .n_ch = 8,
+-	  .mask = FL | FR | RC},
+-	{ .ca_id = 0x05, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RC },
+-	{ .ca_id = 0x06, .n_ch = 8,
+-	  .mask = FL | FR | FC | RC },
+-	{ .ca_id = 0x07, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | RC },
+-	{ .ca_id = 0x0c, .n_ch = 8,
+-	  .mask = FL | FR | RC | RL | RR },
+-	{ .ca_id = 0x0d, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RL | RR | RC },
+-	{ .ca_id = 0x0e, .n_ch = 8,
+-	  .mask = FL | FR | FC | RL | RR | RC },
+-	{ .ca_id = 0x10, .n_ch = 8,
+-	  .mask = FL | FR | RL | RR | RLC | RRC },
+-	{ .ca_id = 0x11, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RL | RR | RLC | RRC },
++	{ .ca_id = 0x1f, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
+ 	{ .ca_id = 0x12, .n_ch = 8,
+ 	  .mask = FL | FR | FC | RL | RR | RLC | RRC },
+-	{ .ca_id = 0x14, .n_ch = 8,
+-	  .mask = FL | FR | FLC | FRC },
+-	{ .ca_id = 0x15, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FLC | FRC },
+-	{ .ca_id = 0x16, .n_ch = 8,
+-	  .mask = FL | FR | FC | FLC | FRC },
+-	{ .ca_id = 0x17, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | FLC | FRC },
+-	{ .ca_id = 0x18, .n_ch = 8,
+-	  .mask = FL | FR | RC | FLC | FRC },
+-	{ .ca_id = 0x19, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RC | FLC | FRC },
+-	{ .ca_id = 0x1a, .n_ch = 8,
+-	  .mask = FL | FR | RC | FC | FLC | FRC },
+-	{ .ca_id = 0x1b, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RC | FC | FLC | FRC },
+-	{ .ca_id = 0x1c, .n_ch = 8,
+-	  .mask = FL | FR | RL | RR | FLC | FRC },
+-	{ .ca_id = 0x1d, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RL | RR | FLC | FRC },
+ 	{ .ca_id = 0x1e, .n_ch = 8,
+ 	  .mask = FL | FR | FC | RL | RR | FLC | FRC },
+-	{ .ca_id = 0x1f, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
++	{ .ca_id = 0x11, .n_ch = 8,
++	  .mask = FL | FR | LFE | RL | RR | RLC | RRC },
++	{ .ca_id = 0x1d, .n_ch = 8,
++	  .mask = FL | FR | LFE | RL | RR | FLC | FRC },
++	{ .ca_id = 0x10, .n_ch = 8,
++	  .mask = FL | FR | RL | RR | RLC | RRC },
++	{ .ca_id = 0x1c, .n_ch = 8,
++	  .mask = FL | FR | RL | RR | FLC | FRC },
++	{ .ca_id = 0x0f, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC | RL | RR | RC },
++	{ .ca_id = 0x1b, .n_ch = 8,
++	  .mask = FL | FR | LFE | RC | FC | FLC | FRC },
++	{ .ca_id = 0x0e, .n_ch = 8,
++	  .mask = FL | FR | FC | RL | RR | RC },
++	{ .ca_id = 0x1a, .n_ch = 8,
++	  .mask = FL | FR | RC | FC | FLC | FRC },
++	{ .ca_id = 0x0d, .n_ch = 8,
++	  .mask = FL | FR | LFE | RL | RR | RC },
++	{ .ca_id = 0x19, .n_ch = 8,
++	  .mask = FL | FR | LFE | RC | FLC | FRC },
++	{ .ca_id = 0x0c, .n_ch = 8,
++	  .mask = FL | FR | RC | RL | RR },
++	{ .ca_id = 0x18, .n_ch = 8,
++	  .mask = FL | FR | RC | FLC | FRC },
++	{ .ca_id = 0x17, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC | FLC | FRC },
++	{ .ca_id = 0x16, .n_ch = 8,
++	  .mask = FL | FR | FC | FLC | FRC },
++	{ .ca_id = 0x15, .n_ch = 8,
++	  .mask = FL | FR | LFE | FLC | FRC },
++	{ .ca_id = 0x14, .n_ch = 8,
++	  .mask = FL | FR | FLC | FRC },
+ };
+ 
+ struct hdmi_codec_priv {

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/HACK-h6-Add-HDMI-sound-card.patch

@@ -0,0 +1,53 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Sat, 16 Jan 2021 10:58:14 +0100
+Subject: [PATCH] HACK: h6: Add HDMI sound card
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20 +++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -108,6 +108,24 @@
+ 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ 	};
+ 
++	sound_hdmi: sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "allwinner-hdmi";
++		simple-audio-card,mclk-fs = <128>;
++		simple-audio-card,frame-inversion;
++
++		simple-audio-card,codec {
++			sound-dai = <&hdmi>;
++		};
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1>;
++			dai-tdm-slot-num = <2>;
++			dai-tdm-slot-width = <32>;
++		};
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+@@ -664,7 +682,6 @@
+ 			dmas = <&dma 4>, <&dma 4>;
+ 			resets = <&ccu RST_BUS_I2S1>;
+ 			dma-names = "rx", "tx";
+-			status = "disabled";
+ 		};
+ 
+ 		spdif: spdif@5093000 {
+@@ -801,6 +818,7 @@
+ 		};
+ 
+ 		hdmi: hdmi@6000000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun50i-h6-dw-hdmi";
+ 			reg = <0x06000000 0x10000>;
+ 			reg-io-width = <1>;

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/Input-axp20x-pek-allow-wakeup-after-shutdown-6_1.patch

@@ -0,0 +1,52 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 2 Jan 2021 15:52:27 -0600
+Subject: [PATCH] Input: axp20x-pek - allow wakeup after shutdown
+
+While the AXP20x PMIC handles the power button itself after shutting
+down, it is not always possible to use the PMIC's built-in shutdown
+feature, such as when other wakeup sources are needed (for example, an
+IR remote or wake-on-LAN) that require firmware support. In that case,
+the PMIC remains on, but suspended, until the board is powered back on.
+
+During this "fake" off state, IRQ configuration is similar to system
+sleep, where enable_irq_wake() must be call on an IRQ for it to be
+wakeup capable. Run the suspend callback to arm the power button IRQs
+during the shutdown process, so the power button works in this state.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/input/misc/axp20x-pek.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+--- a/drivers/input/misc/axp20x-pek.c
++++ b/drivers/input/misc/axp20x-pek.c
+@@ -354,7 +354,7 @@ static int axp20x_pek_probe(struct platf
+ 	return 0;
+ }
+ 
+-static int __maybe_unused axp20x_pek_suspend(struct device *dev)
++static int axp20x_pek_suspend(struct device *dev)
+ {
+ 	struct axp20x_pek *axp20x_pek = dev_get_drvdata(dev);
+ 
+@@ -413,6 +413,11 @@ static const struct dev_pm_ops axp20x_pe
+ #endif
+ };
+ 
++static void axp20x_pek_shutdown(struct platform_device *pdev)
++{
++	axp20x_pek_suspend(&pdev->dev);
++}
++
+ static const struct platform_device_id axp_pek_id_match[] = {
+ 	{
+ 		.name = "axp20x-pek",
+@@ -428,6 +433,7 @@ MODULE_DEVICE_TABLE(platform, axp_pek_id
+ 
+ static struct platform_driver axp20x_pek_driver = {
+ 	.probe		= axp20x_pek_probe,
++	.shutdown	= axp20x_pek_shutdown,
+ 	.id_table	= axp_pek_id_match,
+ 	.driver		= {
+ 		.name		= "axp20x-pek",

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/Input-axp20x-pek-allow-wakeup-after-shutdown-6_5.patch

@@ -0,0 +1,36 @@
+From dbf607d6716dd0a314d734cfd9423601d6c5a99d Mon Sep 17 00:00:00 2001
+From: OpenEmbedded <oe.patch@oe>
+Date: Wed, 6 Dec 2023 18:01:24 +0100
+Subject: [PATCH] Input: axp20x-pek - allow wakeup after shutdown
+
+---
+ drivers/input/misc/axp20x-pek.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/input/misc/axp20x-pek.c b/drivers/input/misc/axp20x-pek.c
+index 4581606a2..7217dc6ed 100644
+--- a/drivers/input/misc/axp20x-pek.c
++++ b/drivers/input/misc/axp20x-pek.c
+@@ -393,6 +393,11 @@ static const struct dev_pm_ops axp20x_pek_pm_ops = {
+ 	.resume_noirq = pm_sleep_ptr(axp20x_pek_resume_noirq),
+ };
+ 
++static void axp20x_pek_shutdown(struct platform_device *pdev)
++{
++	axp20x_pek_suspend(&pdev->dev);
++}
++
+ static const struct platform_device_id axp_pek_id_match[] = {
+ 	{
+ 		.name = "axp20x-pek",
+@@ -408,6 +413,7 @@ MODULE_DEVICE_TABLE(platform, axp_pek_id_match);
+ 
+ static struct platform_driver axp20x_pek_driver = {
+ 	.probe		= axp20x_pek_probe,
++	.shutdown	= axp20x_pek_shutdown,
+ 	.id_table	= axp_pek_id_match,
+ 	.driver		= {
+ 		.name		= "axp20x-pek",
+-- 
+2.43.0
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/OrangePi-3-LTS-support.patch

@@ -0,0 +1,393 @@
+From 20d3d43d9daa82d5fa1e937e17b975974572d189 Mon Sep 17 00:00:00 2001
+From: Juliano Dorigão <jdorigao@gmail.com>
+Date: Fri, 3 Mar 2023 16:12:03 -0400
+Subject: [PATCH] OrangePi 3 LTS support
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../allwinner/sun50i-h6-orangepi-3-lts.dts    | 361 ++++++++++++++++++
+ 2 files changed, 362 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 6a96494a2..ace8159a6 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-beelink-gs1.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3-lts.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+new file mode 100644
+index 000000000..67f38b8a1
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+@@ -0,0 +1,361 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (C) 2023 Jernej Skrabec <jernej.skrabec@gmail.com>
++// Based on sun50i-h6-orangepi-3.dts, which is:
++// Copyright (C) 2019 Ondřej Jirman <megous@megous.com>
++
++/dts-v1/;
++
++#include "sun50i-h6.dtsi"
++#include "sun50i-h6-cpu-opp.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	model = "OrangePi 3 LTS";
++	compatible = "xunlong,orangepi-3-lts", "allwinner,sun50i-h6";
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	ext_osc32k: ext_osc32k_clk {
++		#clock-cells = <0>;
++		compatible = "fixed-clock";
++		clock-frequency = <32768>;
++		clock-output-names = "ext_osc32k";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			label = "orangepi:red:power";
++			gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
++		};
++
++		led-1 {
++			label = "orangepi:green:status";
++			gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
++			default-state = "on";
++		};
++	};
++
++	reg_vcc5v: vcc5v {
++		/* board wide 5V supply directly from the DC jack */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_gmac_3v3: gmac-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "gmac-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <150000>;
++		enable-active-high;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++	};
++
++	reg_vcc33_wifi: vcc33-wifi {
++		/* Always on 3.3V regulator for WiFi and BT */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc33-wifi";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		enable-active-high;
++		gpio = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc33_wifi>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "ext_clock";
++		reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdca>;
++};
++
++&de {
++	status = "okay";
++};
++
++&dwc3 {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ext_rgmii_pins>;
++	phy-mode = "rgmii";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-supply = <&reg_gmac_3v3>;
++	allwinner,rx-delay-ps = <1500>;
++	allwinner,tx-delay-ps = <700>;
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&reg_dcdcc>;
++	status = "okay";
++};
++
++&hdmi {
++	hvcc-supply = <&reg_bldo2>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++
++		reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
++		reset-assert-us = <15000>;
++		reset-deassert-us = <40000>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_cldo1>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
++	bus-width = <4>;
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc33_wifi>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++};
++
++&mmc2 {
++	vmmc-supply = <&reg_cldo1>;
++	vqmmc-supply = <&reg_bldo2>;
++	cap-mmc-hw-reset;
++	non-removable;
++	bus-width = <8>;
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&pio {
++	vcc-pc-supply = <&reg_bldo2>;
++	vcc-pd-supply = <&reg_cldo1>;
++	vcc-pg-supply = <&reg_bldo3>;
++};
++
++&r_ir {
++	status = "okay";
++};
++
++&r_rsb {
++	clock-frequency = <100000>;
++	status = "okay";
++
++	axp805: pmic@745 {
++		compatible = "x-powers,axp805", "x-powers,axp806";
++		reg = <0x745>;
++		interrupt-parent = <&r_intc>;
++		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-controller;
++		#interrupt-cells = <1>;
++		x-powers,self-working-mode;
++		vina-supply = <&reg_vcc5v>;
++		vinb-supply = <&reg_vcc5v>;
++		vinc-supply = <&reg_vcc5v>;
++		vind-supply = <&reg_vcc5v>;
++		vine-supply = <&reg_vcc5v>;
++		aldoin-supply = <&reg_vcc5v>;
++		bldoin-supply = <&reg_vcc5v>;
++		cldoin-supply = <&reg_vcc5v>;
++
++		regulators {
++			reg_aldo1: aldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc-pl-led-ir";
++			};
++
++			reg_aldo2: aldo2 {
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-audio-tv-ephy-mac";
++			};
++
++			/* ALDO3 is shorted to CLDO1 */
++			reg_aldo3: aldo3 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1";
++			};
++
++			reg_bldo1: bldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc18-dram-bias-pll";
++			};
++
++			reg_bldo2: bldo2 {
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc-efuse-pcie-hdmi-pc";
++			};
++
++			reg_bldo3: bldo3 {
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc-pm-pg-dcxoio-wifi";
++			};
++
++			bldo4 {
++				/* unused */
++			};
++
++			reg_cldo1: cldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2";
++			};
++
++			cldo2 {
++				/* unused */
++			};
++
++			cldo3 {
++				/* unused */
++			};
++
++			reg_dcdca: dcdca {
++				regulator-always-on;
++				regulator-min-microvolt = <800000>;
++				regulator-max-microvolt = <1160000>;
++				regulator-ramp-delay = <2500>;
++				regulator-name = "vdd-cpu";
++			};
++
++			reg_dcdcc: dcdcc {
++				regulator-enable-ramp-delay = <32000>;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <1080000>;
++				regulator-ramp-delay = <2500>;
++				regulator-name = "vdd-gpu";
++			};
++
++			reg_dcdcd: dcdcd {
++				regulator-always-on;
++				regulator-min-microvolt = <980000>;
++				regulator-max-microvolt = <980000>;
++				regulator-name = "vdd-sys";
++			};
++
++			reg_dcdce: dcdce {
++				regulator-always-on;
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1200000>;
++				regulator-name = "vcc-dram";
++			};
++
++			sw {
++				/* unused */
++			};
++		};
++	};
++};
++
++&pwm {
++	status = "okay";
++};
++
++&r_ir {
++	status = "okay";
++};
++
++&rtc {
++	clocks = <&ext_osc32k>;
++};
++
++/delete-node/ &spi0;
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&usb2otg {
++	dr_mode = "host";
++	status = "okay";
++};
++
++&usb2phy {
++	usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
++	usb0_vbus-supply = <&reg_vcc5v>;
++	usb3_vbus-supply = <&reg_vcc5v>;
++	status = "okay";
++};
++
++&usb3phy {
++	status = "okay";
++};
+-- 
+2.39.2
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/Revert-clk-qcom-Support-protected-clocks-property.patch

@@ -0,0 +1,49 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 30 Dec 2019 12:39:31 -0600
+Subject: [PATCH] Revert "clk: qcom: Support 'protected-clocks' property"
+
+Now that protected-clocks is handled in the clk core, this
+driver-specific implementation is redundant.
+
+This reverts commit b181b3b801da8893c8eb706e448dd5111b02de60.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/qcom/common.c | 18 ------------------
+ 1 file changed, 18 deletions(-)
+
+--- a/drivers/clk/qcom/common.c
++++ b/drivers/clk/qcom/common.c
+@@ -194,22 +194,6 @@ int qcom_cc_register_sleep_clk(struct de
+ }
+ EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
+ 
+-/* Drop 'protected-clocks' from the list of clocks to register */
+-static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc)
+-{
+-	struct device_node *np = dev->of_node;
+-	struct property *prop;
+-	const __be32 *p;
+-	u32 i;
+-
+-	of_property_for_each_u32(np, "protected-clocks", prop, p, i) {
+-		if (i >= cc->num_rclks)
+-			continue;
+-
+-		cc->rclks[i] = NULL;
+-	}
+-}
+-
+ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
+ 					 void *data)
+ {
+@@ -272,8 +256,6 @@ int qcom_cc_really_probe(struct platform
+ 	cc->rclks = rclks;
+ 	cc->num_rclks = num_clks;
+ 
+-	qcom_cc_drop_protected(dev, cc);
+-
+ 	for (i = 0; i < num_clk_hws; i++) {
+ 		ret = devm_clk_hw_register(dev, clk_hws[i]);
+ 		if (ret)

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch

@@ -0,0 +1,67 @@
+From ba3b30a80ac2c388d48c58fbee242466d51fbfd8 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 6 Dec 2020 11:15:34 -0600
+Subject: [PATCH 177/389] arm64: dts: allwinner: Enforce consistent MMC
+ numbering
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 6 ++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi  | 6 ++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 6 ++++++
+ 3 files changed, 18 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 77b5349f6087..9e0e17179839 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -18,6 +18,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	chosen {
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index a56fae761a1f..2159fa336d75 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -6,6 +6,12 @@
+ #include <dt-bindings/thermal/thermal.h>
+ 
+ / {
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index ca1d287a0a01..3feac99556f3 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -17,6 +17,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+-- 
+2.35.3
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch

@@ -0,0 +1,110 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:40:20 +0200
+Subject: [PATCH] arm64: dts: allwinner: h6: Add AC200 EPHY related nodes
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 56 ++++++++++++++++++++
+ 1 file changed, 56 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -16,6 +16,16 @@
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	ac200_pwm_clk: ac200_clk {
++		compatible = "pwm-clock";
++		#clock-cells = <0>;
++		clock-frequency = <24000000>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pwm1_pin>;
++		pwms = <&pwm 1 42 0>;
++		status = "disabled";
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -319,6 +329,10 @@
+ 			cpu_speed_grade: cpu-speed-grade@1c {
+ 				reg = <0x1c 0x4>;
+ 			};
++
++			ephy_calib: ephy_calib@2c {
++				reg = <0x2c 0x2>;
++			};
+ 		};
+ 
+ 		timer@3009000 {
+@@ -373,6 +387,13 @@
+ 				drive-strength = <40>;
+ 			};
+ 
++			ext_rmii_pins: rmii_pins {
++				pins = "PA0", "PA1", "PA2", "PA3", "PA4",
++				       "PA5", "PA6", "PA7", "PA8", "PA9";
++				function = "emac";
++				drive-strength = <40>;
++			};
++
+ 			hdmi_pins: hdmi-pins {
+ 				pins = "PH8", "PH9", "PH10";
+ 				function = "hdmi";
+@@ -393,6 +414,11 @@
+ 				function = "i2c2";
+ 			};
+ 
++			i2c3_pins: i2c3-pins {
++				pins = "PB17", "PB18";
++				function = "i2c3";
++			};
++
+ 			mmc0_pins: mmc0-pins {
+ 				pins = "PF0", "PF1", "PF2", "PF3",
+ 				       "PF4", "PF5";
+@@ -419,6 +445,11 @@
+ 				bias-pull-up;
+ 			};
+ 
++			pwm1_pin: pwm1-pin {
++				pins = "PB19";
++				function = "pwm1";
++			};
++
+ 			/omit-if-no-ref/
+ 			spi0_pins: spi0-pins {
+ 				pins = "PC0", "PC2", "PC3";
+@@ -652,6 +683,31 @@
+ 			#size-cells = <0>;
+ 		};
+ 
++		i2c3: i2c@5002c00 {
++			compatible = "allwinner,sun6i-a31-i2c";
++			reg = <0x05002c00 0x400>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2C3>;
++			resets = <&ccu RST_BUS_I2C3>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c3_pins>;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			ac200: mfd@10 {
++				compatible = "x-powers,ac200";
++				reg = <0x10>;
++				clocks = <&ac200_pwm_clk>;
++
++				ac200_ephy: phy {
++					compatible = "x-powers,ac200-ephy";
++					nvmem-cells = <&ephy_calib>;
++					nvmem-cell-names = "ephy_calib";
++				};
++			};
++		};
++
+ 		emac: ethernet@5020000 {
+ 			compatible = "allwinner,sun50i-h6-emac",
+ 				     "allwinner,sun50i-a64-emac";

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/arm64-dts-allwinner-h6-Add-SCPI-protocol.patch

@@ -0,0 +1,46 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 14 Dec 2019 20:54:40 -0600
+Subject: [PATCH] arm64: dts: allwinner: h6: Add SCPI protocol
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -88,6 +88,13 @@
+ 		method = "smc";
+ 	};
+ 
++	scpi_protocol: scpi {
++		compatible = "arm,scpi";
++		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mbox-names = "tx", "rx";
++		shmem = <&scpi_sram>;
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		arm,no-tick-in-suspend;
+@@ -196,6 +203,19 @@
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@100000 {
++				compatible = "mmio-sram";
++				reg = <0x00100000 0x18000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00100000 0x18000>;
++
++				scpi_sram: scpi-sram@17c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x17c00 0x200>;
++				};
++			};
++
+ 			sram_c: sram@28000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x00028000 0x1e000>;

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/arm64-dts-allwinner-h6-Fix-Cedrus-IOMMU-again.patch

@@ -0,0 +1,26 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Wed, 12 Oct 2022 23:01:04 +0200
+Subject: [PATCH] arm64: dts: allwinner: h6: Fix Cedrus IOMMU, again
+
+Cedrus actually uses two IOMMU channels. Add the second one.
+
+Fixes: 62a8ccf3a248 ("arm64: dts: allwinner: h6: Fix Cedrus IOMMU usage")
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index e897559d9a89..436cc2a02d1a 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -172,7 +172,7 @@ video-codec@1c0e000 {
+ 			resets = <&ccu RST_BUS_VE>;
+ 			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ 			allwinner,sram = <&ve_sram 1>;
+-			iommus = <&iommu 3>;
++			iommus = <&iommu 1>, <&iommu 3>;
+ 		};
+ 
+ 		gpu: gpu@1800000 {

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/arm64-dts-h6-deinterlace.patch

@@ -0,0 +1,31 @@
+From c009b3b707bbde30fa6ff49ca3075160524ea7b9 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Tue, 26 May 2020 20:08:27 +0200
+Subject: [PATCH 41/44] arm64: dts: h6 deinterlace
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -160,6 +160,18 @@
+ 			};
+ 		};
+
++		deinterlace: deinterlace@1420000 {
++			compatible = "allwinner,sun50i-h6-deinterlace";
++			reg = <0x01420000 0x2000>;
++			clocks = <&ccu CLK_BUS_DEINTERLACE>,
++				 <&ccu CLK_DEINTERLACE>,
++				 <&ccu CLK_MBUS_DEINTERLACE>;
++			clock-names = "bus", "mod", "ram";
++			resets = <&ccu RST_BUS_DEINTERLACE>;
++			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
++			iommus = <&iommu 2>;
++		};
++
+ 		video-codec@1c0e000 {
+ 			compatible = "allwinner,sun50i-h6-video-engine";
+ 			reg = <0x01c0e000 0x2000>;

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/clk-Implement-protected-clocks-for-all-OF-clock-prov.patch

@@ -0,0 +1,197 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 29 Dec 2019 20:23:28 -0600
+Subject: [PATCH] clk: Implement protected-clocks for all OF clock providers
+
+This is a generic implementation of the "protected-clocks" property from
+the common clock binding. It allows firmware to inform the OS about
+clocks that must not be disabled while the OS is running.
+
+This implementation comes with some caveats:
+
+1) Clocks that have CLK_IS_CRITICAL in their init data are prepared/
+enabled before they are attached to the clock tree. protected-clocks are
+only protected once the clock provider is added, which is generally
+after all of the clocks it provides have been registered. This leaves a
+window of opportunity where something could disable or modify the clock,
+such as a driver running on another CPU, or the clock core itself. There
+is a comment to this effect in __clk_core_init():
+
+  /*
+   * Enable CLK_IS_CRITICAL clocks so newly added critical clocks
+   * don't get accidentally disabled when walking the orphan tree and
+   * reparenting clocks
+   */
+
+Similarly, these clocks will be enabled after they are first reparented,
+unlike other CLK_IS_CRITICAL clocks. See the comment in
+clk_core_reparent_orphans_nolock():
+
+  /*
+   * We need to use __clk_set_parent_before() and _after() to
+   * to properly migrate any prepare/enable count of the orphan
+   * clock. This is important for CLK_IS_CRITICAL clocks, which
+   * are enabled during init but might not have a parent yet.
+   */
+
+Ideally we could detect protected clocks before they are reparented, but
+there are two problems with that:
+
+  a) From the clock core's perspective, hw->init is const.
+
+  b) The clock core doesn't see the device_node until __clk_register is
+     called on the first clock.
+
+So the only "race-free" way to detect protected-clocks is to do it in
+the middle of __clk_register, between when core->flags is initialized
+and calling __clk_core_init(). That requires scanning the device tree
+again for each clock, which is part of why I didn't do it that way.
+
+2) __clk_protect needs to be idempotent, for two reasons:
+
+  a) Clocks with CLK_IS_CRITICAL in their init data are already
+     prepared/enabled, and we don't want to prepare/enable them again.
+
+  b) of_clk_set_defaults() is called twice for (at least some) clock
+     controllers registered with CLK_OF_DECLARE. It is called first in
+     of_clk_add_provider()/of_clk_add_hw_provider() inside clk_init_cb,
+     and again afterward in of_clk_init(). The second call in
+     of_clk_init() may be unnecessary, but verifying that would require
+     auditing all users of CLK_OF_DECLARE to ensure they called one of
+     the of_clk_add{,_hw}_provider functions.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/clk-conf.c | 54 ++++++++++++++++++++++++++++++++++++++++++
+ drivers/clk/clk.c      | 31 ++++++++++++++++++++++++
+ drivers/clk/clk.h      |  2 ++
+ 3 files changed, 87 insertions(+)
+
+--- a/drivers/clk/clk-conf.c
++++ b/drivers/clk/clk-conf.c
+@@ -11,6 +11,54 @@
+ #include <linux/of.h>
+ #include <linux/printk.h>
+ 
++#include "clk.h"
++
++static int __set_clk_flags(struct device_node *node)
++{
++	struct of_phandle_args clkspec;
++	struct property *prop;
++	int i, index = 0, rc;
++	const __be32 *cur;
++	struct clk *clk;
++	u32 nr_cells;
++
++	rc = of_property_read_u32(node, "#clock-cells", &nr_cells);
++	if (rc < 0) {
++		pr_err("clk: missing #clock-cells property on %pOF\n", node);
++		return rc;
++	}
++
++	clkspec.np         = node;
++	clkspec.args_count = nr_cells;
++
++	of_property_for_each_u32(node, "protected-clocks", prop, cur, clkspec.args[0]) {
++		/* read the remainder of the clock specifier */
++		for (i = 1; i < nr_cells; ++i) {
++			cur = of_prop_next_u32(prop, cur, &clkspec.args[i]);
++			if (!cur) {
++				pr_err("clk: invalid value of protected-clocks"
++				       " property at %pOF\n", node);
++				return -EINVAL;
++			}
++		}
++		clk = of_clk_get_from_provider(&clkspec);
++		if (IS_ERR(clk)) {
++			if (PTR_ERR(clk) != -EPROBE_DEFER)
++				pr_err("clk: couldn't get protected clock"
++				       " %u for %pOF\n", index, node);
++			return PTR_ERR(clk);
++		}
++
++		rc = __clk_protect(clk);
++		if (rc < 0)
++			pr_warn("clk: failed to protect %s: %d\n",
++				__clk_get_name(clk), rc);
++		clk_put(clk);
++		index++;
++	}
++	return 0;
++}
++
+ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
+ {
+ 	struct of_phandle_args clkspec;
+@@ -135,6 +183,12 @@ int of_clk_set_defaults(struct device_no
+ 	if (!node)
+ 		return 0;
+ 
++	if (clk_supplier) {
++		rc = __set_clk_flags(node);
++		if (rc < 0)
++			return rc;
++	}
++
+ 	rc = __set_clk_parents(node, clk_supplier);
+ 	if (rc < 0)
+ 		return rc;
+--- a/drivers/clk/clk.c
++++ b/drivers/clk/clk.c
+@@ -4271,6 +4271,37 @@ struct clk *devm_clk_hw_get_clk(struct d
+ EXPORT_SYMBOL_GPL(devm_clk_hw_get_clk);
+ 
+ /*
++ * clk-conf helpers
++ */
++
++int __clk_protect(struct clk *clk)
++{
++	struct clk_core *core = clk->core;
++	int ret = 0;
++
++	clk_prepare_lock();
++
++	/*
++	 * If CLK_IS_CRITICAL was set in the clock's init data, then
++	 * the clock was already prepared/enabled when it was added.
++	 */
++	if (core->flags & CLK_IS_CRITICAL)
++		goto out;
++
++	core->flags |= CLK_IS_CRITICAL;
++	ret = clk_core_prepare(core);
++	if (ret)
++		goto out;
++
++	ret = clk_core_enable_lock(core);
++
++out:
++	clk_prepare_unlock();
++
++	return ret;
++}
++
++/*
+  * clkdev helpers
+  */
+ 
+--- a/drivers/clk/clk.h
++++ b/drivers/clk/clk.h
+@@ -24,6 +24,7 @@ struct clk_hw *clk_find_hw(const char *d
+ #ifdef CONFIG_COMMON_CLK
+ struct clk *clk_hw_create_clk(struct device *dev, struct clk_hw *hw,
+ 			      const char *dev_id, const char *con_id);
++int __clk_protect(struct clk *clk);
+ void __clk_put(struct clk *clk);
+ #else
+ /* All these casts to avoid ifdefs in clkdev... */
+@@ -33,6 +34,7 @@ clk_hw_create_clk(struct device *dev, st
+ {
+ 	return (struct clk *)hw;
+ }
++static inline int __clk_protect(struct clk *clk) { return 0; }
+ static inline void __clk_put(struct clk *clk) { }
+ 
+ #endif

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch

@@ -0,0 +1,122 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 5 Mar 2019 22:02:41 -0600
+Subject: [PATCH] firmware: arm_scpi: Support unidirectional mailbox channels
+
+Some mailbox controllers have only unidirectional channels, so we need a
+pair of them for each SCPI channel. If a mbox-names property is present,
+look for "rx" and "tx" mbox channels; otherwise, the existing behavior
+is preserved, and a single mbox channel is used for each SCPI channel.
+
+Note that since the mailbox framework only supports a single phandle
+with each name (mbox_request_channel_byname always returns the first
+one), this new mode only supports a single SCPI channel.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/firmware/arm_scpi.c | 58 +++++++++++++++++++++++++++++--------
+ 1 file changed, 46 insertions(+), 12 deletions(-)
+
+--- a/drivers/firmware/arm_scpi.c
++++ b/drivers/firmware/arm_scpi.c
+@@ -231,7 +231,8 @@ struct scpi_xfer {
+ 
+ struct scpi_chan {
+ 	struct mbox_client cl;
+-	struct mbox_chan *chan;
++	struct mbox_chan *rx_chan;
++	struct mbox_chan *tx_chan;
+ 	void __iomem *tx_payload;
+ 	void __iomem *rx_payload;
+ 	struct list_head rx_pending;
+@@ -505,7 +506,7 @@ static int scpi_send_message(u8 idx, voi
+ 	msg->rx_len = rx_len;
+ 	reinit_completion(&msg->done);
+ 
+-	ret = mbox_send_message(scpi_chan->chan, msg);
++	ret = mbox_send_message(scpi_chan->tx_chan, msg);
+ 	if (ret < 0 || !rx_buf)
+ 		goto out;
+ 
+@@ -856,8 +857,13 @@ static void scpi_free_channels(void *dat
+ 	struct scpi_drvinfo *info = data;
+ 	int i;
+ 
+-	for (i = 0; i < info->num_chans; i++)
+-		mbox_free_channel(info->channels[i].chan);
++	for (i = 0; i < info->num_chans; i++) {
++		struct scpi_chan *pchan = &info->channels[i];
++
++		if (pchan->tx_chan != pchan->rx_chan)
++			mbox_free_channel(pchan->tx_chan);
++		mbox_free_channel(pchan->rx_chan);
++	}
+ }
+ 
+ static int scpi_remove(struct platform_device *pdev)
+@@ -913,6 +919,7 @@ static int scpi_probe(struct platform_de
+ 	struct device *dev = &pdev->dev;
+ 	struct device_node *np = dev->of_node;
+ 	struct scpi_drvinfo *scpi_drvinfo;
++	bool use_mbox_names = false;
+ 
+ 	scpi_drvinfo = devm_kzalloc(dev, sizeof(*scpi_drvinfo), GFP_KERNEL);
+ 	if (!scpi_drvinfo)
+@@ -926,6 +933,14 @@ static int scpi_probe(struct platform_de
+ 		dev_err(dev, "no mboxes property in '%pOF'\n", np);
+ 		return -ENODEV;
+ 	}
++	if (of_get_property(dev->of_node, "mbox-names", NULL)) {
++		use_mbox_names = true;
++		if (count != 2) {
++			dev_err(dev, "need exactly 2 mboxes with mbox-names\n");
++			return -ENODEV;
++		}
++		count /= 2;
++	}
+ 
+ 	scpi_info->channels = devm_kcalloc(dev, count, sizeof(struct scpi_chan),
+ 					   GFP_KERNEL);
+@@ -974,15 +989,34 @@ static int scpi_probe(struct platform_de
+ 		mutex_init(&pchan->xfers_lock);
+ 
+ 		ret = scpi_alloc_xfer_list(dev, pchan);
+-		if (!ret) {
+-			pchan->chan = mbox_request_channel(cl, idx);
+-			if (!IS_ERR(pchan->chan))
+-				continue;
+-			ret = PTR_ERR(pchan->chan);
+-			if (ret != -EPROBE_DEFER)
+-				dev_err(dev, "failed to get channel%d err %d\n",
+-					idx, ret);
++		if (ret)
++			return ret;
++
++		if (use_mbox_names) {
++			pchan->rx_chan = mbox_request_channel_byname(cl, "rx");
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->rx_chan);
++				goto fail;
++			}
++			pchan->tx_chan = mbox_request_channel_byname(cl, "tx");
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->tx_chan);
++				goto fail;
++			}
++		} else {
++			pchan->rx_chan = mbox_request_channel(cl, idx);
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->rx_chan);
++				goto fail;
++			}
++			pchan->tx_chan = pchan->rx_chan;
+ 		}
++		continue;
++
++fail:
++		if (ret != -EPROBE_DEFER)
++			dev_err(dev, "failed to get channel%d err %d\n",
++				idx, ret);
+ 		return ret;
+ 	}
+ 

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/fix-orange-pi-3lts-rtc-on-faulty-boards.patch

@@ -0,0 +1,29 @@
+From 791849a059cce08f238491b8cae1c3d452edcda5 Mon Sep 17 00:00:00 2001
+From: OpenEmbedded <oe.patch@oe>
+Date: Wed, 6 Dec 2023 00:37:25 +0100
+Subject: [PATCH 1/2] fix orange pi 3lts rtc on faulty boards"
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+index 67f38b8a1..e3337c6f2 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+@@ -331,10 +331,10 @@ &pwm {
+ &r_ir {
+ 	status = "okay";
+ };
+-
++/*
+ &rtc {
+ 	clocks = <&ext_osc32k>;
+-};
++};*/
+ 
+ /delete-node/ &spi0;
+ 
+-- 
+2.43.0
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/fix-rtc.scc

@@ -0,0 +1,3 @@
+# Optional patch for 3 lts that deactivates external 32Khz crystals and fallback to internal clock
+# This fix rtc problems at the cost of clock accuracy on faulty boards
+patch fix-orange-pi-3lts-rtc-on-faulty-boards.patch

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/iommu-sun50i-Allow-page-sizes-multiple-of-4096.patch

@@ -0,0 +1,107 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Fri, 14 Oct 2022 20:15:43 +0200
+Subject: [PATCH] iommu/sun50i: Allow page sizes multiple of 4096
+
+While peripheral supports only 4K page sizes, we can easily emulate
+support for bigger page sizes, up to 1M. This is done by making multiple
+entries in map function or clearing multiple entries in unmap.
+
+This considerably lowers overhead.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/iommu/sun50i-iommu.c | 44 +++++++++++++++++++++---------------
+ 1 file changed, 26 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
+index d7c5e9b1a087..9944266c4f58 100644
+--- a/drivers/iommu/sun50i-iommu.c
++++ b/drivers/iommu/sun50i-iommu.c
+@@ -593,10 +593,12 @@ static int sun50i_iommu_map(struct iommu_domain *domain, unsigned long iova,
+ {
+ 	struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain);
+ 	struct sun50i_iommu *iommu = sun50i_domain->iommu;
+-	u32 pte_index;
++	u32 pte_index, pages, i;
+ 	u32 *page_table, *pte_addr;
+ 	int ret = 0;
+ 
++	pages = size / SPAGE_SIZE;
++
+ 	page_table = sun50i_dte_get_page_table(sun50i_domain, iova, gfp);
+ 	if (IS_ERR(page_table)) {
+ 		ret = PTR_ERR(page_table);
+@@ -604,18 +606,21 @@ static int sun50i_iommu_map(struct iommu_domain *domain, unsigned long iova,
+ 	}
+ 
+ 	pte_index = sun50i_iova_get_pte_index(iova);
+-	pte_addr = &page_table[pte_index];
+-	if (unlikely(sun50i_pte_is_page_valid(*pte_addr))) {
+-		phys_addr_t page_phys = sun50i_pte_get_page_address(*pte_addr);
+-		dev_err(iommu->dev,
+-			"iova %pad already mapped to %pa cannot remap to %pa prot: %#x\n",
+-			&iova, &page_phys, &paddr, prot);
+-		ret = -EBUSY;
+-		goto out;
++	for (i = 0; i < pages; i++) {
++		pte_addr = &page_table[pte_index + i];
++		if (unlikely(sun50i_pte_is_page_valid(*pte_addr))) {
++			phys_addr_t page_phys = sun50i_pte_get_page_address(*pte_addr);
++			dev_err(iommu->dev,
++				"iova %pad already mapped to %pa cannot remap to %pa prot: %#x\n",
++				&iova, &page_phys, &paddr, prot);
++			ret = -EBUSY;
++			goto out;
++		}
++		*pte_addr = sun50i_mk_pte(paddr, prot);
++		paddr += SPAGE_SIZE;
+ 	}
+ 
+-	*pte_addr = sun50i_mk_pte(paddr, prot);
+-	sun50i_table_flush(sun50i_domain, pte_addr, 1);
++	sun50i_table_flush(sun50i_domain, &page_table[pte_index], pages);
+ 
+ out:
+ 	return ret;
+@@ -626,8 +631,10 @@ static size_t sun50i_iommu_unmap(struct iommu_domain *domain, unsigned long iova
+ {
+ 	struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain);
+ 	phys_addr_t pt_phys;
++	u32 dte, pages, i;
+ 	u32 *pte_addr;
+-	u32 dte;
++
++	pages = size / SPAGE_SIZE;
+ 
+ 	dte = sun50i_domain->dt[sun50i_iova_get_dte_index(iova)];
+ 	if (!sun50i_dte_is_pt_valid(dte))
+@@ -636,13 +643,14 @@ static size_t sun50i_iommu_unmap(struct iommu_domain *domain, unsigned long iova
+ 	pt_phys = sun50i_dte_get_pt_address(dte);
+ 	pte_addr = (u32 *)phys_to_virt(pt_phys) + sun50i_iova_get_pte_index(iova);
+ 
+-	if (!sun50i_pte_is_page_valid(*pte_addr))
+-		return 0;
++	for (i = 0; i < pages; i++)
++		if (!sun50i_pte_is_page_valid(pte_addr[i]))
++			return 0;
+ 
+-	memset(pte_addr, 0, sizeof(*pte_addr));
+-	sun50i_table_flush(sun50i_domain, pte_addr, 1);
++	memset(pte_addr, 0, sizeof(*pte_addr) * pages);
++	sun50i_table_flush(sun50i_domain, pte_addr, pages);
+ 
+-	return SZ_4K;
++	return size;
+ }
+ 
+ static phys_addr_t sun50i_iommu_iova_to_phys(struct iommu_domain *domain,
+@@ -828,7 +836,7 @@ static int sun50i_iommu_of_xlate(struct device *dev,
+ }
+ 
+ static const struct iommu_ops sun50i_iommu_ops = {
+-	.pgsize_bitmap	= SZ_4K,
++	.pgsize_bitmap	= 0x1ff000,
+ 	.device_group	= sun50i_iommu_device_group,
+ 	.domain_alloc	= sun50i_iommu_domain_alloc,
+ 	.of_xlate	= sun50i_iommu_of_xlate,

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/mfd-Add-support-for-AC200.patch

@@ -0,0 +1,406 @@
+From 59adceb6f34521c0f1a229f20ee9961269daa539 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:38:21 +0200
+Subject: [PATCH 38/44] mfd: Add support for AC200
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/mfd/Kconfig       |   9 ++
+ drivers/mfd/Makefile      |   1 +
+ drivers/mfd/ac200.c       | 150 +++++++++++++++++++++++++++
+ include/linux/mfd/ac200.h | 209 ++++++++++++++++++++++++++++++++++++++
+ 4 files changed, 369 insertions(+)
+ create mode 100644 drivers/mfd/ac200.c
+ create mode 100644 include/linux/mfd/ac200.h
+
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -178,6 +178,15 @@ config MFD_AC100
+ 	  This driver include only the core APIs. You have to select individual
+ 	  components like codecs or RTC under the corresponding menus.
+ 
++config MFD_AC200
++	tristate "X-Powers AC200"
++	select MFD_CORE
++	depends on I2C
++	help
++	  If you say Y here you get support for the X-Powers AC200 IC.
++	  This driver include only the core APIs. You have to select individual
++	  components like Ethernet PHY or RTC under the corresponding menus.
++
+ config MFD_AXP20X
+ 	tristate
+ 	select MFD_CORE
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -142,6 +142,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)	+= da9052-s
+ obj-$(CONFIG_MFD_DA9052_I2C)	+= da9052-i2c.o
+ 
+ obj-$(CONFIG_MFD_AC100)		+= ac100.o
++obj-$(CONFIG_MFD_AC200)		+= ac200.o
+ obj-$(CONFIG_MFD_AXP20X)	+= axp20x.o
+ obj-$(CONFIG_MFD_AXP20X_I2C)	+= axp20x-i2c.o
+ obj-$(CONFIG_MFD_AXP20X_RSB)	+= axp20x-rsb.o
+--- /dev/null
++++ b/drivers/mfd/ac200.c
+@@ -0,0 +1,148 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * MFD core driver for X-Powers' AC200 IC
++ *
++ * The AC200 is a chip which is co-packaged with Allwinner H6 SoC and
++ * includes analog audio codec, analog TV encoder, ethernet PHY, eFuse
++ * and RTC.
++ *
++ * Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
++ *
++ * Based on AC100 driver with following copyrights:
++ * Copyright (2016) Chen-Yu Tsai
++ */
++
++#include <linux/i2c.h>
++#include <linux/kernel.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/ac200.h>
++#include <linux/module.h>
++#include <linux/of.h>
++
++static const struct regmap_range_cfg ac200_range_cfg[] = {
++	{
++		.range_min = AC200_SYS_VERSION,
++		.range_max = AC200_IC_CHARA1,
++		.selector_reg = AC200_TWI_REG_ADDR_H,
++		.selector_mask = 0xff,
++		.selector_shift = 0,
++		.window_start = 0,
++		.window_len = 256,
++	}
++};
++
++static const struct regmap_config ac200_regmap_config = {
++	.reg_bits	= 8,
++	.val_bits	= 16,
++	.ranges		= ac200_range_cfg,
++	.num_ranges	= ARRAY_SIZE(ac200_range_cfg),
++	.max_register	= AC200_IC_CHARA1,
++};
++
++static struct mfd_cell ac200_cells[] = {
++	{
++		.name		= "ac200-codec",
++		.of_compatible	= "x-powers,ac200-codec",
++	}, {
++		.name		= "ac200-efuse",
++		.of_compatible	= "x-powers,ac200-efuse",
++	}, {
++		.name		= "ac200-ephy",
++		.of_compatible	= "x-powers,ac200-ephy",
++	}, {
++		.name		= "ac200-rtc",
++		.of_compatible	= "x-powers,ac200-rtc",
++	}, {
++		.name		= "ac200-tve",
++		.of_compatible	= "x-powers,ac200-tve",
++	},
++};
++
++static int ac200_i2c_probe(struct i2c_client *i2c,
++			   const struct i2c_device_id *id)
++{
++	struct device *dev = &i2c->dev;
++	struct ac200_dev *ac200;
++	int ret;
++
++	ac200 = devm_kzalloc(dev, sizeof(*ac200), GFP_KERNEL);
++	if (!ac200)
++		return -ENOMEM;
++
++	i2c_set_clientdata(i2c, ac200);
++
++	ac200->clk = devm_clk_get(dev, NULL);
++	if (IS_ERR(ac200->clk)) {
++		ret = PTR_ERR(ac200->clk);
++		dev_err(dev, "Can't obtain the clock: %d\n", ret);
++		return ret;
++	}
++
++	ac200->regmap = devm_regmap_init_i2c(i2c, &ac200_regmap_config);
++	if (IS_ERR(ac200->regmap)) {
++		ret = PTR_ERR(ac200->regmap);
++		dev_err(dev, "Regmap init failed: %d\n", ret);
++		return ret;
++	}
++
++	ret = clk_prepare_enable(ac200->clk);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++	if (ret)
++		goto err;
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 1);
++	if (ret)
++		goto err;
++
++	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, ac200_cells,
++				   ARRAY_SIZE(ac200_cells), NULL, 0, NULL);
++	if (ret) {
++		dev_err(dev, "Failed to add MFD devices: %d\n", ret);
++		goto err;
++	}
++
++	return 0;
++
++err:
++	clk_disable_unprepare(ac200->clk);
++	return ret;
++}
++
++void ac200_i2c_remove(struct i2c_client *i2c)
++{
++	struct ac200_dev *ac200 = i2c_get_clientdata(i2c);
++
++	regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++
++	clk_disable_unprepare(ac200->clk);
++}
++
++static const struct i2c_device_id ac200_ids[] = {
++	{ "ac200", },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(i2c, ac200_ids);
++
++static const struct of_device_id ac200_of_match[] = {
++	{ .compatible = "x-powers,ac200" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ac200_of_match);
++
++static struct i2c_driver ac200_i2c_driver = {
++	.driver = {
++		.name	= "ac200",
++		.of_match_table	= of_match_ptr(ac200_of_match),
++	},
++	.probe	= ac200_i2c_probe,
++	.remove = ac200_i2c_remove,
++	.id_table = ac200_ids,
++};
++module_i2c_driver(ac200_i2c_driver);
++
++MODULE_DESCRIPTION("MFD core driver for AC200");
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/include/linux/mfd/ac200.h
+@@ -0,0 +1,209 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * AC200 register list
++ *
++ * Copyright (C) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
++ */
++
++#ifndef __LINUX_MFD_AC200_H
++#define __LINUX_MFD_AC200_H
++
++#include <linux/clk.h>
++#include <linux/regmap.h>
++
++/* interface registers (can be accessed from any page) */
++#define AC200_TWI_CHANGE_TO_RSB		0x3E
++#define AC200_TWI_PAD_DELAY		0xC4
++#define AC200_TWI_REG_ADDR_H		0xFE
++
++/* General registers */
++#define AC200_SYS_VERSION		0x0000
++#define AC200_SYS_CONTROL		0x0002
++#define AC200_SYS_IRQ_ENABLE		0x0004
++#define AC200_SYS_IRQ_STATUS		0x0006
++#define AC200_SYS_CLK_CTL		0x0008
++#define AC200_SYS_DLDO_OSC_CTL		0x000A
++#define AC200_SYS_PLL_CTL0		0x000C
++#define AC200_SYS_PLL_CTL1		0x000E
++#define AC200_SYS_AUDIO_CTL0		0x0010
++#define AC200_SYS_AUDIO_CTL1		0x0012
++#define AC200_SYS_EPHY_CTL0		0x0014
++#define AC200_SYS_EPHY_CTL1		0x0016
++#define AC200_SYS_TVE_CTL0		0x0018
++#define AC200_SYS_TVE_CTL1		0x001A
++
++/* Audio Codec registers */
++#define AC200_AC_SYS_CLK_CTL		0x2000
++#define AC200_SYS_MOD_RST		0x2002
++#define AC200_SYS_SAMP_CTL		0x2004
++#define AC200_I2S_CTL			0x2100
++#define AC200_I2S_CLK			0x2102
++#define AC200_I2S_FMT0			0x2104
++#define AC200_I2S_FMT1			0x2108
++#define AC200_I2S_MIX_SRC		0x2114
++#define AC200_I2S_MIX_GAIN		0x2116
++#define AC200_I2S_DACDAT_DVC		0x2118
++#define AC200_I2S_ADCDAT_DVC		0x211A
++#define AC200_AC_DAC_DPC		0x2200
++#define AC200_AC_DAC_MIX_SRC		0x2202
++#define AC200_AC_DAC_MIX_GAIN		0x2204
++#define AC200_DACA_OMIXER_CTRL		0x2220
++#define AC200_OMIXER_SR			0x2222
++#define AC200_LINEOUT_CTRL		0x2224
++#define AC200_AC_ADC_DPC		0x2300
++#define AC200_MBIAS_CTRL		0x2310
++#define AC200_ADC_MIC_CTRL		0x2320
++#define AC200_ADCMIXER_SR		0x2322
++#define AC200_ANALOG_TUNING0		0x232A
++#define AC200_ANALOG_TUNING1		0x232C
++#define AC200_AC_AGC_SEL		0x2480
++#define AC200_ADC_DAPLCTRL		0x2500
++#define AC200_ADC_DAPRCTRL		0x2502
++#define AC200_ADC_DAPLSTA		0x2504
++#define AC200_ADC_DAPRSTA		0x2506
++#define AC200_ADC_DAPLTL		0x2508
++#define AC200_ADC_DAPRTL		0x250A
++#define AC200_ADC_DAPLHAC		0x250C
++#define AC200_ADC_DAPLLAC		0x250E
++#define AC200_ADC_DAPRHAC		0x2510
++#define AC200_ADC_DAPRLAC		0x2512
++#define AC200_ADC_DAPLDT		0x2514
++#define AC200_ADC_DAPLAT		0x2516
++#define AC200_ADC_DAPRDT		0x2518
++#define AC200_ADC_DAPRAT		0x251A
++#define AC200_ADC_DAPNTH		0x251C
++#define AC200_ADC_DAPLHNAC		0x251E
++#define AC200_ADC_DAPLLNAC		0x2520
++#define AC200_ADC_DAPRHNAC		0x2522
++#define AC200_ADC_DAPRLNAC		0x2524
++#define AC200_AC_DAPHHPFC		0x2526
++#define AC200_AC_DAPLHPFC		0x2528
++#define AC200_AC_DAPOPT			0x252A
++#define AC200_AC_DAC_DAPCTRL		0x3000
++#define AC200_AC_DRC_HHPFC		0x3002
++#define AC200_AC_DRC_LHPFC		0x3004
++#define AC200_AC_DRC_CTRL		0x3006
++#define AC200_AC_DRC_LPFHAT		0x3008
++#define AC200_AC_DRC_LPFLAT		0x300A
++#define AC200_AC_DRC_RPFHAT		0x300C
++#define AC200_AC_DRC_RPFLAT		0x300E
++#define AC200_AC_DRC_LPFHRT		0x3010
++#define AC200_AC_DRC_LPFLRT		0x3012
++#define AC200_AC_DRC_RPFHRT		0x3014
++#define AC200_AC_DRC_RPFLRT		0x3016
++#define AC200_AC_DRC_LRMSHAT		0x3018
++#define AC200_AC_DRC_LRMSLAT		0x301A
++#define AC200_AC_DRC_RRMSHAT		0x301C
++#define AC200_AC_DRC_RRMSLAT		0x301E
++#define AC200_AC_DRC_HCT		0x3020
++#define AC200_AC_DRC_LCT		0x3022
++#define AC200_AC_DRC_HKC		0x3024
++#define AC200_AC_DRC_LKC		0x3026
++#define AC200_AC_DRC_HOPC		0x3028
++#define AC200_AC_DRC_LOPC		0x302A
++#define AC200_AC_DRC_HLT		0x302C
++#define AC200_AC_DRC_LLT		0x302E
++#define AC200_AC_DRC_HKI		0x3030
++#define AC200_AC_DRC_LKI		0x3032
++#define AC200_AC_DRC_HOPL		0x3034
++#define AC200_AC_DRC_LOPL		0x3036
++#define AC200_AC_DRC_HET		0x3038
++#define AC200_AC_DRC_LET		0x303A
++#define AC200_AC_DRC_HKE		0x303C
++#define AC200_AC_DRC_LKE		0x303E
++#define AC200_AC_DRC_HOPE		0x3040
++#define AC200_AC_DRC_LOPE		0x3042
++#define AC200_AC_DRC_HKN		0x3044
++#define AC200_AC_DRC_LKN		0x3046
++#define AC200_AC_DRC_SFHAT		0x3048
++#define AC200_AC_DRC_SFLAT		0x304A
++#define AC200_AC_DRC_SFHRT		0x304C
++#define AC200_AC_DRC_SFLRT		0x304E
++#define AC200_AC_DRC_MXGHS		0x3050
++#define AC200_AC_DRC_MXGLS		0x3052
++#define AC200_AC_DRC_MNGHS		0x3054
++#define AC200_AC_DRC_MNGLS		0x3056
++#define AC200_AC_DRC_EPSHC		0x3058
++#define AC200_AC_DRC_EPSLC		0x305A
++#define AC200_AC_DRC_HPFHGAIN		0x305E
++#define AC200_AC_DRC_HPFLGAIN		0x3060
++#define AC200_AC_DRC_BISTCR		0x3100
++#define AC200_AC_DRC_BISTST		0x3102
++
++/* TVE registers */
++#define AC200_TVE_CTL0			0x4000
++#define AC200_TVE_CTL1			0x4002
++#define AC200_TVE_MOD0			0x4004
++#define AC200_TVE_MOD1			0x4006
++#define AC200_TVE_DAC_CFG0		0x4008
++#define AC200_TVE_DAC_CFG1		0x400A
++#define AC200_TVE_YC_DELAY		0x400C
++#define AC200_TVE_YC_FILTER		0x400E
++#define AC200_TVE_BURST_FRQ0		0x4010
++#define AC200_TVE_BURST_FRQ1		0x4012
++#define AC200_TVE_FRONT_PORCH		0x4014
++#define AC200_TVE_BACK_PORCH		0x4016
++#define AC200_TVE_TOTAL_LINE		0x401C
++#define AC200_TVE_FIRST_ACTIVE		0x401E
++#define AC200_TVE_BLACK_LEVEL		0x4020
++#define AC200_TVE_BLANK_LEVEL		0x4022
++#define AC200_TVE_PLUG_EN		0x4030
++#define AC200_TVE_PLUG_IRQ_EN		0x4032
++#define AC200_TVE_PLUG_IRQ_STA		0x4034
++#define AC200_TVE_PLUG_STA		0x4038
++#define AC200_TVE_PLUG_DEBOUNCE		0x4040
++#define AC200_TVE_DAC_TEST		0x4042
++#define AC200_TVE_PLUG_PULSE_LEVEL	0x40F4
++#define AC200_TVE_PLUG_PULSE_START	0x40F8
++#define AC200_TVE_PLUG_PULSE_PERIOD	0x40FA
++#define AC200_TVE_IF_CTL		0x5000
++#define AC200_TVE_IF_TIM0		0x5008
++#define AC200_TVE_IF_TIM1		0x500A
++#define AC200_TVE_IF_TIM2		0x500C
++#define AC200_TVE_IF_TIM3		0x500E
++#define AC200_TVE_IF_SYNC0		0x5010
++#define AC200_TVE_IF_SYNC1		0x5012
++#define AC200_TVE_IF_SYNC2		0x5014
++#define AC200_TVE_IF_TIM4		0x5016
++#define AC200_TVE_IF_STATUS		0x5018
++
++/* EPHY registers */
++#define AC200_EPHY_CTL			0x6000
++#define AC200_EPHY_BIST			0x6002
++
++/* eFuse registers (0x8000 - 0x9FFF, layout unknown) */
++
++/* RTC registers */
++#define AC200_LOSC_CTRL0		0xA000
++#define AC200_LOSC_CTRL1		0xA002
++#define AC200_LOSC_AUTO_SWT_STA		0xA004
++#define AC200_INTOSC_CLK_PRESCAL	0xA008
++#define AC200_RTC_YY_MM_DD0		0xA010
++#define AC200_RTC_YY_MM_DD1		0xA012
++#define AC200_RTC_HH_MM_SS0		0xA014
++#define AC200_RTC_HH_MM_SS1		0xA016
++#define AC200_ALARM0_CUR_VLU0		0xA024
++#define AC200_ALARM0_CUR_VLU1		0xA026
++#define AC200_ALARM0_ENABLE		0xA028
++#define AC200_ALARM0_IRQ_EN		0xA02C
++#define AC200_ALARM0_IRQ_STA		0xA030
++#define AC200_ALARM1_WK_HH_MM_SS0	0xA040
++#define AC200_ALARM1_WK_HH_MM_SS1	0xA042
++#define AC200_ALARM1_ENABLE		0xA044
++#define AC200_ALARM1_IRQ_EN		0xA048
++#define AC200_ALARM1_IRQ_STA		0xA04C
++#define AC200_ALARM_CONFIG		0xA050
++#define AC200_LOSC_OUT_GATING		0xA060
++#define AC200_GP_DATA(x)		(0xA100 + (x) * 2)
++#define AC200_RTC_DEB			0xA170
++#define AC200_GPL_HOLD_OUTPUT		0xA180
++#define AC200_VDD_RTC			0xA190
++#define AC200_IC_CHARA0			0xA1F0
++#define AC200_IC_CHARA1			0xA1F2
++
++struct ac200_dev {
++	struct clk	*clk;
++	struct regmap	*regmap;
++};
++
++#endif /* __LINUX_MFD_AC200_H */

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch

@@ -0,0 +1,374 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 13 Jun 2022 17:37:19 +0100
+Subject: mfd: Add support for X-Powers AC200 EPHY syscon
+
+The X-Powers AC200 mixed signal chip contains a 100Mbit/s Ethernet PHY.
+While the PHY is using the standard MDIO and MII/RMII interfaces to
+the MAC, there are some registers in the AC200 that need to be setup to
+make the PHY functional:
+- The MDIO PHY address needs to set.
+- The LED polarity needs to be configured.
+- The MII interface mode needs to be set (MII or RMII).
+- There is a reset line that controls the PHY operation.
+- There is a clock gate that blocks or forwards the AC200's internal clock
+  to the PHY.
+
+This driver here takes care of those setup needs, but does not cover the
+actual PHY operation. Once the PHY is set up and enabled, it behaves like
+a standard MDIO/MII controlled PHY, and can be driven by the IEEE802.3-C22
+driver.
+
+To some degree those parameters mimic the typical wired setup of a
+physical PHY chip: the LED polarity, MII interface mode and PHY address
+are typically configued via connecting certain pins. We use the
+devicetree to learn those parameters, which depend on the board setup.
+
+This driver is a child of the AC200 MFD parent device, and uses its
+regmap and input clock. It also provides a reset and clock controller,
+which the actual PHY device (node) needs to refer to. This ensures that
+this PHY control device is initialised before the PHY is expected to work.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/phy/allwinner/Kconfig          |   9 +
+ drivers/phy/allwinner/Makefile         |   1 +
+ drivers/phy/allwinner/ac200-ephy-ctl.c | 301 ++++++++++
+ 3 files changed, 311 insertions(+)
+
+diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
+index e93a53139460..d3614169de5c 100644
+--- a/drivers/phy/allwinner/Kconfig
++++ b/drivers/phy/allwinner/Kconfig
+@@ -58,3 +58,12 @@ config PHY_SUN50I_USB3
+ 	  part of Allwinner H6 SoC.
+ 
+ 	  This driver controls each individual USB 2+3 host PHY combo.
++
++config AC200_PHY_CTL
++	tristate "X-Power AC200 PHY control driver"
++	depends on MFD_AC200
++	depends on RESET_CONTROLLER
++	help
++	  Enable this to support the Ethernet PHY operation of the AC200
++	  mixed signal chip. This driver just enables and configures the
++	  PHY, the PHY itself is supported by a standard driver.
+diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile
+index bd74901a1255..0eecec7a908a 100644
+--- a/drivers/phy/allwinner/Makefile
++++ b/drivers/phy/allwinner/Makefile
+@@ -3,3 +3,4 @@ obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
+ obj-$(CONFIG_PHY_SUN6I_MIPI_DPHY)	+= phy-sun6i-mipi-dphy.o
+ obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
+ obj-$(CONFIG_PHY_SUN50I_USB3)		+= phy-sun50i-usb3.o
++obj-$(CONFIG_AC200_PHY_CTL)		+= ac200-ephy-ctl.o
+diff --git a/drivers/phy/allwinner/ac200-ephy-ctl.c b/drivers/phy/allwinner/ac200-ephy-ctl.c
+new file mode 100644
+index 000000000000..8efeaf18e42c
+--- /dev/null
++++ b/drivers/phy/allwinner/ac200-ephy-ctl.c
+@@ -0,0 +1,301 @@
++// SPDX-License-Identifier: GPL-2.0+
++/**
++ * syscon driver to control and configure AC200 Ethernet PHY
++ * Copyright (c) 2022 Arm Ltd.
++ *
++ * TODO's and questions:
++ * =========================
++ * - This driver is something like a syscon driver, as it controls various
++ *   bits and registers that effect other devices (the actual PHY). It's
++ *   unclear where it should live, though:
++ *   - it could be integrated into the MFD driver, but this looks messy
++ *   - it could live at the current location (drivers/phy/allwinner), but that
++ *     sounds wrong
++ *   - it could be a separate file, but in drivers/mfd
++ *   - anything else
++ *
++ */
++
++#include <dt-bindings/gpio/gpio.h>
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of.h>
++#include <linux/of_net.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
++#include <linux/reset-controller.h>
++
++/* macros for system ephy control 0 register */
++#define AC200_SYS_EPHY_CTL0		0x0014
++#define AC200_EPHY_RESET_INVALID	BIT(0)
++#define AC200_EPHY_SYSCLK_GATING	1
++
++/* macros for system ephy control 1 register */
++#define AC200_SYS_EPHY_CTL1		0x0016
++#define AC200_EPHY_E_EPHY_MII_IO_EN	BIT(0)
++#define AC200_EPHY_E_LNK_LED_IO_EN	BIT(1)
++#define AC200_EPHY_E_SPD_LED_IO_EN	BIT(2)
++#define AC200_EPHY_E_DPX_LED_IO_EN	BIT(3)
++
++/* macros for ephy control register */
++#define AC200_EPHY_CTL			0x6000
++#define AC200_EPHY_SHUTDOWN		BIT(0)
++#define AC200_EPHY_LED_POL		BIT(1)
++#define AC200_EPHY_CLK_SEL		BIT(2)
++#define AC200_EPHY_ADDR(x)		(((x) & 0x1F) << 4)
++#define AC200_EPHY_XMII_SEL		BIT(11)
++#define AC200_EPHY_CALIB(x)		(((x) & 0xF) << 12)
++
++struct ac200_ephy_ctl_dev {
++	struct reset_controller_dev	rcdev;
++	struct clk_hw			*gate_clk;
++	struct regmap			*regmap;
++};
++
++static struct ac200_ephy_ctl_dev *to_phy_dev(struct reset_controller_dev *rcdev)
++{
++	return container_of(rcdev, struct ac200_ephy_ctl_dev, rcdev);
++}
++
++static int ephy_ctl_reset(struct reset_controller_dev *rcdev, unsigned long id)
++{
++	struct ac200_ephy_ctl_dev *ac200 = to_phy_dev(rcdev);
++	int ret;
++
++	ret = regmap_clear_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++				AC200_EPHY_RESET_INVALID);
++	if (ret)
++		return ret;
++
++	/* This is going via I2C, so there is plenty of built-in delay. */
++	return regmap_set_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++			       AC200_EPHY_RESET_INVALID);
++}
++
++static int ephy_ctl_assert(struct reset_controller_dev *rcdev, unsigned long id)
++{
++	struct ac200_ephy_ctl_dev *ac200 = to_phy_dev(rcdev);
++
++	return regmap_clear_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++				 AC200_EPHY_RESET_INVALID);
++}
++
++static int ephy_ctl_deassert(struct reset_controller_dev *rcdev,
++			     unsigned long id)
++{
++	struct ac200_ephy_ctl_dev *ac200 = to_phy_dev(rcdev);
++
++	return regmap_set_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++			       AC200_EPHY_RESET_INVALID);
++}
++
++static int ephy_ctl_status(struct reset_controller_dev *rcdev, unsigned long id)
++{
++	struct ac200_ephy_ctl_dev *ac200 = to_phy_dev(rcdev);
++
++	return regmap_test_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++				AC200_EPHY_RESET_INVALID);
++}
++
++static int ephy_ctl_reset_of_xlate(struct reset_controller_dev *rcdev,
++				   const struct of_phandle_args *reset_spec)
++{
++	if (WARN_ON(reset_spec->args_count != 0))
++		return -EINVAL;
++
++	return 0;
++}
++
++const struct reset_control_ops ephy_ctl_reset_ops = {
++	.assert		= ephy_ctl_assert,
++	.deassert	= ephy_ctl_deassert,
++	.reset		= ephy_ctl_reset,
++	.status		= ephy_ctl_status,
++};
++
++static void ac200_ephy_ctl_disable(struct ac200_ephy_ctl_dev *priv)
++{
++	regmap_write(priv->regmap, AC200_EPHY_CTL, AC200_EPHY_SHUTDOWN);
++	regmap_write(priv->regmap, AC200_SYS_EPHY_CTL1, 0);
++	regmap_write(priv->regmap, AC200_SYS_EPHY_CTL0, 0);
++}
++
++static int ac200_ephy_ctl_probe(struct platform_device *pdev)
++{
++	struct reset_controller_dev *rcdev;
++	struct device *dev = &pdev->dev;
++	struct ac200_ephy_ctl_dev *priv;
++	struct nvmem_cell *calcell;
++	const char *parent_name;
++	phy_interface_t phy_if;
++	u16 *caldata, ephy_ctl;
++	struct clk *clk;
++	size_t callen;
++	u32 value;
++	int ret;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, priv);
++
++	priv->regmap = dev_get_regmap(dev->parent, NULL);
++	if (!priv->regmap)
++		return -EPROBE_DEFER;
++
++	calcell = devm_nvmem_cell_get(dev, "calibration");
++	if (IS_ERR(calcell))
++		return dev_err_probe(dev, PTR_ERR(calcell),
++				     "Unable to find calibration data!\n");
++
++	caldata = nvmem_cell_read(calcell, &callen);
++	if (IS_ERR(caldata)) {
++		dev_err(dev, "Unable to read calibration data!\n");
++		return PTR_ERR(caldata);
++	}
++
++	if (callen != 2) {
++		dev_err(dev, "Calibration data length must be 2 bytes!\n");
++		kfree(caldata);
++		return -EINVAL;
++	}
++
++	ephy_ctl = AC200_EPHY_CALIB(*caldata + 3);
++	kfree(caldata);
++
++	ret = of_get_phy_mode(dev->of_node, &phy_if);
++	if (ret) {
++		dev_err(dev, "Unable to read PHY connection mode\n");
++		return ret;
++	}
++
++	switch (phy_if) {
++	case PHY_INTERFACE_MODE_MII:
++		break;
++	case PHY_INTERFACE_MODE_RMII:
++		ephy_ctl |= AC200_EPHY_XMII_SEL;
++		break;
++	default:
++		dev_err(dev, "Illegal PHY connection mode (%d), only RMII or MII supported\n",
++			phy_if);
++		return -EINVAL;
++	}
++
++	ret = of_property_read_u32(dev->of_node, "x-powers,led-polarity",
++				   &value);
++	if (ret) {
++		dev_err(dev, "Unable to read LED polarity setting\n");
++		return ret;
++	}
++
++	if (value == GPIO_ACTIVE_LOW)
++		ephy_ctl |= AC200_EPHY_LED_POL;
++
++	ret = of_property_read_u32(dev->of_node, "phy-address", &value);
++	if (ret) {
++		dev_err(dev, "Unable to read PHY address value\n");
++		return ret;
++	}
++
++	ephy_ctl |= AC200_EPHY_ADDR(value);
++
++	clk = clk_get(dev->parent, NULL);
++	if (IS_ERR(clk))
++		return dev_err_probe(dev, PTR_ERR(clk),
++				     "Unable to obtain the clock\n");
++
++	if (clk_get_rate(clk) == 24000000)
++		ephy_ctl |= AC200_EPHY_CLK_SEL;
++
++	clk_put(clk);
++
++	/* Assert reset and gate clock, to disable PHY for now */
++	ret = regmap_write(priv->regmap, AC200_SYS_EPHY_CTL0, 0);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(priv->regmap, AC200_SYS_EPHY_CTL1,
++			   AC200_EPHY_E_EPHY_MII_IO_EN |
++			   AC200_EPHY_E_LNK_LED_IO_EN |
++			   AC200_EPHY_E_SPD_LED_IO_EN |
++			   AC200_EPHY_E_DPX_LED_IO_EN);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(priv->regmap, AC200_EPHY_CTL, ephy_ctl);
++	if (ret)
++		return ret;
++
++	rcdev = &priv->rcdev;
++	rcdev->owner = dev->driver->owner;
++	rcdev->nr_resets = 1;
++	rcdev->ops = &ephy_ctl_reset_ops;
++	rcdev->of_node = dev->of_node;
++	rcdev->of_reset_n_cells = 0;
++	rcdev->of_xlate = ephy_ctl_reset_of_xlate;
++
++	ret = devm_reset_controller_register(dev, rcdev);
++	if (ret) {
++		dev_err(dev, "Unable to register reset controller: %d\n", ret);
++		goto err_disable_ephy;
++	}
++
++	parent_name = of_clk_get_parent_name(dev->parent->of_node, 0);
++	priv->gate_clk = devm_clk_hw_register_regmap_gate(dev,
++				"ac200-ephy-ctl-gate", parent_name, 0,
++				priv->regmap, AC200_SYS_EPHY_CTL0,
++				AC200_EPHY_SYSCLK_GATING, 0);
++	if (IS_ERR(priv->gate_clk)) {
++		ret = PTR_ERR(priv->gate_clk);
++		dev_err(dev, "Unable to register gate clock: %d\n", ret);
++		goto err_disable_ephy;
++	}
++
++	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
++					  priv->gate_clk);
++	if (ret) {
++		dev_err(dev, "Unable to register clock provider: %d\n", ret);
++		goto err_disable_ephy;
++	}
++
++	return 0;
++
++err_disable_ephy:
++	ac200_ephy_ctl_disable(priv);
++
++	return ret;
++}
++
++static int ac200_ephy_ctl_remove(struct platform_device *pdev)
++{
++	struct ac200_ephy_ctl_dev *priv = platform_get_drvdata(pdev);
++
++	ac200_ephy_ctl_disable(priv);
++
++	return 0;
++}
++
++static const struct of_device_id ac200_ephy_ctl_match[] = {
++	{ .compatible = "x-powers,ac200-ephy-ctl" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ac200_ephy_ctl_match);
++
++static struct platform_driver ac200_ephy_ctl_driver = {
++	.probe		= ac200_ephy_ctl_probe,
++	.remove		= ac200_ephy_ctl_remove,
++	.driver		= {
++		.name		= "ac200-ephy-ctl",
++		.of_match_table	= ac200_ephy_ctl_match,
++	},
++};
++module_platform_driver(ac200_ephy_ctl_driver);
++
++MODULE_AUTHOR("Andre Przywara <andre.przywara@arm.com>");
++MODULE_DESCRIPTION("AC200 Ethernet PHY control driver");
++MODULE_LICENSE("GPL");
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/mfd-Add-support-for-X-Powers-AC200.patch

@@ -0,0 +1,265 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:38:21 +0200
+Subject: mfd: Add support for X-Powers AC200
+
+The X-Powers AC200 is a mixed signal multi-purpose chip, which provides
+audio DAC/ADCs, a CVBS video encoder, a 100Mbit/s Ethernet PHY and a
+real-time clock. Its control registers can be accessed via I2C or
+Allwinner's RSB bus.
+Beside this chip being used on some older boards (for instance the Remix
+Mini PC), it is quite wide spread due to its die being co-packaged on the
+Allwinner H6 and H616 SoCs, which use its audio, video and PHY
+functionality.
+
+Aside from the RTC, the other functions do not need constant
+hand-holding via the I2C registers, but rather need to be configured and
+enabled only once.
+
+We model the control side of this chip using the MFD subsystem. This
+driver here just provides the parent device for the various subfunctions,
+and takes care of enabling clocks and reset, but also provides the regmap,
+which the respective child drivers will use.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/mfd/Kconfig  |  12 +
+ drivers/mfd/Makefile |   1 +
+ drivers/mfd/ac200.c  | 190 ++++++++++
+ 3 files changed, 203 insertions(+)
+
+diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
+index f6b519eaaa71..39fef6420fe5 100644
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -191,6 +191,18 @@ config MFD_AC100
+ 	  This driver include only the core APIs. You have to select individual
+ 	  components like codecs or RTC under the corresponding menus.
+ 
++config MFD_AC200
++	tristate "X-Powers AC200"
++	select MFD_CORE
++	select REGMAP_I2C
++	depends on COMMON_CLK
++	depends on I2C
++	depends on OF
++	help
++	  If you say Y here you get support for the X-Powers AC200 IC.
++	  This driver include only the core APIs. You have to select individual
++	  components like Ethernet PHY or codec under the corresponding menus.
++
+ config MFD_AXP20X
+ 	tristate
+ 	select MFD_CORE
+diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
+index f3d1f1dc73b5..e2ba77bd1d51 100644
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -137,6 +137,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)	+= da9052-spi.o
+ obj-$(CONFIG_MFD_DA9052_I2C)	+= da9052-i2c.o
+ 
+ obj-$(CONFIG_MFD_AC100)		+= ac100.o
++obj-$(CONFIG_MFD_AC200)		+= ac200.o
+ obj-$(CONFIG_MFD_AXP20X)	+= axp20x.o
+ obj-$(CONFIG_MFD_AXP20X_I2C)	+= axp20x-i2c.o
+ obj-$(CONFIG_MFD_AXP20X_RSB)	+= axp20x-rsb.o
+diff --git a/drivers/mfd/ac200.c b/drivers/mfd/ac200.c
+new file mode 100644
+index 000000000000..ad28c380c880
+--- /dev/null
++++ b/drivers/mfd/ac200.c
+@@ -0,0 +1,190 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * MFD core driver for X-Powers' AC200 IC
++ *
++ * The AC200 is a chip which is co-packaged with Allwinner H6 SoC and
++ * includes analog audio codec, analog TV encoder, ethernet PHY, eFuse
++ * and RTC.
++ *
++ * Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@gmail.com>
++ *
++ * Based on AC100 driver with following copyrights:
++ * Copyright (2016) Chen-Yu Tsai
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/i2c.h>
++#include <linux/kernel.h>
++#include <linux/mfd/core.h>
++#include <linux/module.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of.h>
++#include <linux/regmap.h>
++
++struct ac200_dev {
++	struct clk	*clk;
++	struct regmap	*regmap;
++};
++
++#define AC200_SYS_CONTROL	0x0002
++#define AC200_SYS_BG_CTL	0x0050
++
++/* interface register (can be accessed from any page) */
++#define AC200_TWI_REG_ADDR_H	0xFE
++
++#define AC200_MAX_REG		0xA1F2
++
++static const struct regmap_range_cfg ac200_range_cfg[] = {
++	{
++		.range_max = AC200_MAX_REG,
++		.selector_reg = AC200_TWI_REG_ADDR_H,
++		.selector_mask = 0xff,
++		.selector_shift = 0,
++		.window_start = 0,
++		.window_len = 256,
++	}
++};
++
++static const struct regmap_config ac200_regmap_config = {
++	.name		= "AC200",
++	.reg_bits	= 8,
++	.reg_stride	= 2,
++	.val_bits	= 16,
++	.ranges		= ac200_range_cfg,
++	.num_ranges	= ARRAY_SIZE(ac200_range_cfg),
++	.max_register	= AC200_MAX_REG,
++};
++
++static struct mfd_cell ac200_cells[] = {
++	{
++		.name		= "ac200-codec",
++		.of_compatible	= "x-powers,ac200-codec",
++	}, {
++		.name		= "ac200-ephy-ctl",
++		.of_compatible	= "x-powers,ac200-ephy-ctl",
++	},
++};
++
++static int ac200_i2c_probe(struct i2c_client *i2c)
++{
++	struct device *dev = &i2c->dev;
++	struct nvmem_cell *bgcell;
++	struct ac200_dev *ac200;
++	u16 *bgdata, bgval;
++	size_t bglen;
++	int ret;
++
++	ac200 = devm_kzalloc(dev, sizeof(*ac200), GFP_KERNEL);
++	if (!ac200)
++		return -ENOMEM;
++
++	i2c_set_clientdata(i2c, ac200);
++
++	ac200->clk = devm_clk_get(dev, NULL);
++	if (IS_ERR(ac200->clk))
++		return dev_err_probe(dev, PTR_ERR(ac200->clk),
++				     "Can't obtain the clock\n");
++
++	ac200->regmap = devm_regmap_init_i2c(i2c, &ac200_regmap_config);
++	if (IS_ERR(ac200->regmap)) {
++		ret = PTR_ERR(ac200->regmap);
++		dev_err(dev, "Regmap init failed: %d\n", ret);
++		return ret;
++	}
++
++	bgcell = devm_nvmem_cell_get(dev, "bandgap");
++	if (IS_ERR(bgcell))
++		return dev_err_probe(dev, PTR_ERR(bgcell),
++				     "Unable to find bandgap data!\n");
++
++	bgdata = nvmem_cell_read(bgcell, &bglen);
++	if (IS_ERR(bgdata)) {
++		dev_err(dev, "Unable to read bandgap data!\n");
++		return PTR_ERR(bgdata);
++	}
++
++	if (bglen != 2) {
++		dev_err(dev, "Invalid nvmem bandgap length!\n");
++		kfree(bgdata);
++		return -EINVAL;
++	}
++
++	bgval = *bgdata;
++	kfree(bgdata);
++
++	ret = clk_prepare_enable(ac200->clk);
++	if (ret)
++		return ret;
++
++	/*
++	 * There is no documentation on how long we have to wait before
++	 * executing first operation. Vendor driver sleeps for 40 ms.
++	 */
++	msleep(40);
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++	if (ret)
++		goto err;
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 1);
++	if (ret)
++		goto err;
++
++	if (bgval) {
++		/* bandgap register is not documented */
++		ret = regmap_write(ac200->regmap, AC200_SYS_BG_CTL,
++				   0x8280 | bgval);
++		if (ret)
++			goto err;
++	}
++
++	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, ac200_cells,
++				   ARRAY_SIZE(ac200_cells), NULL, 0, NULL);
++	if (ret) {
++		dev_err(dev, "Failed to add MFD devices: %d\n", ret);
++		goto err;
++	}
++
++	return 0;
++
++err:
++	clk_disable_unprepare(ac200->clk);
++	return ret;
++}
++
++static void ac200_i2c_remove(struct i2c_client *i2c)
++{
++	struct ac200_dev *ac200 = i2c_get_clientdata(i2c);
++
++	regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++
++	clk_disable_unprepare(ac200->clk);
++}
++
++static const struct i2c_device_id ac200_ids[] = {
++	{ "ac200", },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ac200_ids);
++
++static const struct of_device_id ac200_of_match[] = {
++	{ .compatible = "x-powers,ac200" },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ac200_of_match);
++
++static struct i2c_driver ac200_i2c_driver = {
++	.driver = {
++		.name	= "ac200",
++		.of_match_table	= of_match_ptr(ac200_of_match),
++	},
++	.probe	= ac200_i2c_probe,
++	.remove = ac200_i2c_remove,
++	.id_table = ac200_ids,
++};
++module_i2c_driver(ac200_i2c_driver);
++
++MODULE_DESCRIPTION("MFD core driver for AC200");
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@gmail.com>");
++MODULE_LICENSE("GPL v2");
+-- 
+Armbian
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch

@@ -0,0 +1,60 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Alejandro=20Gonz=C3=A1lez?=
+ <alejandro.gonzalez.correo@gmail.com>
+Date: Sun, 25 Aug 2019 17:05:58 +0200
+Subject: [PATCH] mmc: sunxi: fix unusuable eMMC on some H6 boards by disabling
+ DDR
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Some Allwinner H6 boards have timing problems when dealing with
+DDR-capable eMMC cards. These boards include the Pine H64 and Tanix TX6.
+
+These timing problems result in out of sync communication between the
+driver and the eMMC, which renders the memory unsuable for every
+operation but some basic commmands, like reading the status register.
+
+The cause of these timing problems is not yet well known, but they go
+away by disabling DDR mode operation in the driver. Like on some H5
+boards, it might be that the traces are not precise enough to support
+these speeds. However, Jernej Skrabec compared the BSP driver with this
+driver, and found that the BSP driver configures pinctrl to operate at
+1.8 V when entering DDR mode (although 3.3 V operation is supported), while
+the mainline kernel lacks any mechanism to switch voltages dynamically.
+Finally, other possible cause might be some timing parameter that is
+different on the H6 with respect to other SoCs.
+
+Therefore, as this fix works reliably, the kernel lacks the required
+dynamic pinctrl control for now and a slow eMMC is better than a not
+working eMMC, just disable DDR operation for now on H6-compatible
+devices.
+
+Signed-off-by: Alejandro González <alejandro.gonzalez.correo@gmail.com>
+---
+ drivers/mmc/host/sunxi-mmc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -1421,14 +1421,17 @@ static int sunxi_mmc_probe(struct platfo
+ 
+ 	/*
+ 	 * Some H5 devices do not have signal traces precise enough to
+-	 * use HS DDR mode for their eMMC chips.
++	 * use HS DDR mode for their eMMC chips. Other H6 devices operate
++	 * unreliably on HS DDR mode, too.
+ 	 *
+ 	 * We still enable HS DDR modes for all the other controller
+-	 * variants that support them.
++	 * variants that support them properly.
+ 	 */
+ 	if ((host->cfg->clk_delays || host->use_new_timings) &&
+ 	    !of_device_is_compatible(pdev->dev.of_node,
+-				     "allwinner,sun50i-h5-emmc"))
++				     "allwinner,sun50i-h5-emmc") &&
++	    !of_device_is_compatible(pdev->dev.of_node,
++				     "allwinner,sun50i-h6-emmc"))
+ 		mmc->caps      |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
+ 
+ 	ret = mmc_of_parse(mmc);

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/net-phy-Add-support-for-AC200-EPHY.patch

@@ -0,0 +1,276 @@
+From cbf68fb141747879e2e6c43584c1e1e3b4d77683 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:38:57 +0200
+Subject: [PATCH 39/44] net: phy: Add support for AC200 EPHY
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/net/phy/Kconfig  |   7 ++
+ drivers/net/phy/Makefile |   1 +
+ drivers/net/phy/ac200.c  | 234 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 242 insertions(+)
+ create mode 100644 drivers/net/phy/ac200.c
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -63,6 +63,13 @@ config SFP
+ 
+ comment "MII PHY device drivers"
+ 
++config AC200_PHY
++	tristate "AC200 EPHY"
++	depends on NVMEM
++	depends on OF
++	help
++	  Fast ethernet PHY as found in X-Powers AC200 multi-function device.
++
+ config AMD_PHY
+ 	tristate "AMD PHYs"
+ 	help
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -30,6 +30,7 @@ obj-$(CONFIG_SFP)		+= sfp.o
+ sfp-obj-$(CONFIG_SFP)		+= sfp-bus.o
+ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
+ 
++obj-$(CONFIG_AC200_PHY)		+= ac200.o
+ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_AMD_PHY)		+= amd.o
+ aquantia-objs			+= aquantia_main.o
+--- /dev/null
++++ b/drivers/net/phy/ac200.c
+@@ -0,0 +1,234 @@
++// SPDX-License-Identifier: GPL-2.0+
++/**
++ * Driver for AC200 Ethernet PHY
++ *
++ * Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mfd/ac200.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
++
++#define AC200_EPHY_ID			0x00441400
++#define AC200_EPHY_ID_MASK		0x0ffffff0
++
++/* macros for system ephy control 0 register */
++#define AC200_EPHY_RESET_INVALID	BIT(0)
++#define AC200_EPHY_SYSCLK_GATING	BIT(1)
++
++/* macros for system ephy control 1 register */
++#define AC200_EPHY_E_EPHY_MII_IO_EN	BIT(0)
++#define AC200_EPHY_E_LNK_LED_IO_EN	BIT(1)
++#define AC200_EPHY_E_SPD_LED_IO_EN	BIT(2)
++#define AC200_EPHY_E_DPX_LED_IO_EN	BIT(3)
++
++/* macros for ephy control register */
++#define AC200_EPHY_SHUTDOWN		BIT(0)
++#define AC200_EPHY_LED_POL		BIT(1)
++#define AC200_EPHY_CLK_SEL		BIT(2)
++#define AC200_EPHY_ADDR(x)		(((x) & 0x1F) << 4)
++#define AC200_EPHY_XMII_SEL		BIT(11)
++#define AC200_EPHY_CALIB(x)		(((x) & 0xF) << 12)
++
++struct ac200_ephy_dev {
++	struct phy_driver	*ephy;
++	struct regmap		*regmap;
++};
++
++static char *ac200_phy_name = "AC200 EPHY";
++
++static void disable_intelligent_ieee(struct phy_device *phydev)
++{
++	unsigned int value;
++
++	phy_write(phydev, 0x1f, 0x0100);	/* switch to page 1 */
++	value = phy_read(phydev, 0x17);
++	value &= ~BIT(3);			/* disable IEEE */
++	phy_write(phydev, 0x17, value);
++	phy_write(phydev, 0x1f, 0x0000);	/* switch to page 0 */
++}
++
++static void disable_802_3az_ieee(struct phy_device *phydev)
++{
++	unsigned int value;
++
++	phy_write(phydev, 0xd, 0x7);
++	phy_write(phydev, 0xe, 0x3c);
++	phy_write(phydev, 0xd, BIT(14) | 0x7);
++	value = phy_read(phydev, 0xe);
++	value &= ~BIT(1);
++	phy_write(phydev, 0xd, 0x7);
++	phy_write(phydev, 0xe, 0x3c);
++	phy_write(phydev, 0xd, BIT(14) | 0x7);
++	phy_write(phydev, 0xe, value);
++
++	phy_write(phydev, 0x1f, 0x0200);	/* switch to page 2 */
++	phy_write(phydev, 0x18, 0x0000);
++}
++
++static int ac200_ephy_config_init(struct phy_device *phydev)
++{
++	const struct ac200_ephy_dev *priv = phydev->drv->driver_data;
++	unsigned int value;
++	int ret;
++
++	phy_write(phydev, 0x1f, 0x0100);	/* Switch to Page 1 */
++	phy_write(phydev, 0x12, 0x4824);	/* Disable APS */
++
++	phy_write(phydev, 0x1f, 0x0200);	/* Switch to Page 2 */
++	phy_write(phydev, 0x18, 0x0000);	/* PHYAFE TRX optimization */
++
++	phy_write(phydev, 0x1f, 0x0600);	/* Switch to Page 6 */
++	phy_write(phydev, 0x14, 0x708f);	/* PHYAFE TX optimization */
++	phy_write(phydev, 0x13, 0xF000);	/* PHYAFE RX optimization */
++	phy_write(phydev, 0x15, 0x1530);
++
++	phy_write(phydev, 0x1f, 0x0800);	/* Switch to Page 6 */
++	phy_write(phydev, 0x18, 0x00bc);	/* PHYAFE TRX optimization */
++
++	disable_intelligent_ieee(phydev);	/* Disable Intelligent IEEE */
++	disable_802_3az_ieee(phydev);		/* Disable 802.3az IEEE */
++	phy_write(phydev, 0x1f, 0x0000);	/* Switch to Page 0 */
++
++	value = (phydev->interface == PHY_INTERFACE_MODE_RMII) ?
++		AC200_EPHY_XMII_SEL : 0;
++	ret = regmap_update_bits(priv->regmap, AC200_EPHY_CTL,
++				 AC200_EPHY_XMII_SEL, value);
++	if (ret)
++		return ret;
++
++	/* FIXME: This is probably H6 specific */
++	value = phy_read(phydev, 0x13);
++	value |= BIT(12);
++	phy_write(phydev, 0x13, value);
++
++	return 0;
++}
++
++static const struct mdio_device_id __maybe_unused ac200_ephy_phy_tbl[] = {
++	{ AC200_EPHY_ID, AC200_EPHY_ID_MASK },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(mdio, ac200_ephy_phy_tbl);
++
++static int ac200_ephy_probe(struct platform_device *pdev)
++{
++	struct ac200_dev *ac200 = dev_get_drvdata(pdev->dev.parent);
++	struct device *dev = &pdev->dev;
++	struct ac200_ephy_dev *priv;
++	struct nvmem_cell *calcell;
++	struct phy_driver *ephy;
++	u16 *caldata, calib;
++	size_t callen;
++	int ret;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	ephy = devm_kzalloc(dev, sizeof(*ephy), GFP_KERNEL);
++	if (!ephy)
++		return -ENOMEM;
++
++	calcell = devm_nvmem_cell_get(dev, "ephy_calib");
++	if (IS_ERR(calcell)) {
++		dev_err(dev, "Unable to find calibration data!\n");
++		return PTR_ERR(calcell);
++	}
++
++	caldata = nvmem_cell_read(calcell, &callen);
++	if (IS_ERR(caldata)) {
++		dev_err(dev, "Unable to read calibration data!\n");
++		return PTR_ERR(caldata);
++	}
++
++	if (callen != 2) {
++		dev_err(dev, "Calibration data has wrong length: 2 != %lu\n",
++			callen);
++		kfree(caldata);
++		return -EINVAL;
++	}
++
++	calib = *caldata + 3;
++	kfree(caldata);
++
++	ephy->phy_id = AC200_EPHY_ID;
++	ephy->phy_id_mask = AC200_EPHY_ID_MASK;
++	ephy->name = ac200_phy_name;
++	ephy->driver_data = priv;
++	ephy->soft_reset = genphy_soft_reset;
++	ephy->config_init = ac200_ephy_config_init;
++	ephy->suspend = genphy_suspend;
++	ephy->resume = genphy_resume;
++
++	priv->ephy = ephy;
++	priv->regmap = ac200->regmap;
++	platform_set_drvdata(pdev, priv);
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_EPHY_CTL0,
++			   AC200_EPHY_RESET_INVALID |
++			   AC200_EPHY_SYSCLK_GATING);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_EPHY_CTL1,
++			   AC200_EPHY_E_EPHY_MII_IO_EN |
++			   AC200_EPHY_E_LNK_LED_IO_EN |
++			   AC200_EPHY_E_SPD_LED_IO_EN |
++			   AC200_EPHY_E_DPX_LED_IO_EN);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(ac200->regmap, AC200_EPHY_CTL,
++			   AC200_EPHY_LED_POL |
++			   AC200_EPHY_CLK_SEL |
++			   AC200_EPHY_ADDR(1) |
++			   AC200_EPHY_CALIB(calib));
++	if (ret)
++		return ret;
++
++	ret = phy_driver_register(priv->ephy, THIS_MODULE);
++	if (ret) {
++		dev_err(dev, "Unable to register phy\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static int ac200_ephy_remove(struct platform_device *pdev)
++{
++	struct ac200_ephy_dev *priv = platform_get_drvdata(pdev);
++
++	phy_driver_unregister(priv->ephy);
++
++	regmap_write(priv->regmap, AC200_EPHY_CTL, AC200_EPHY_SHUTDOWN);
++	regmap_write(priv->regmap, AC200_SYS_EPHY_CTL1, 0);
++	regmap_write(priv->regmap, AC200_SYS_EPHY_CTL0, 0);
++
++	return 0;
++}
++
++static const struct of_device_id ac200_ephy_match[] = {
++	{ .compatible = "x-powers,ac200-ephy" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ac200_ephy_match);
++
++static struct platform_driver ac200_ephy_driver = {
++	.probe		= ac200_ephy_probe,
++	.remove		= ac200_ephy_remove,
++	.driver		= {
++		.name		= "ac200-ephy",
++		.of_match_table	= ac200_ephy_match,
++	},
++};
++module_platform_driver(ac200_ephy_driver);
++
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
++MODULE_DESCRIPTION("AC200 Ethernet PHY driver");
++MODULE_LICENSE("GPL");

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/orange-pi-3lts-6_1.scc

@@ -0,0 +1,8 @@
+# K metadata for orangepi lts
+#  version 6.1 
+
+patch Input-axp20x-pek-allow-wakeup-after-shutdown-6_1.patch
+patch mfd-Add-support-for-AC200.patch                 
+patch net-phy-Add-support-for-AC200-EPHY.patch
+
+include orange-pi-3lts-common.scc

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/orange-pi-3lts-6_5.scc

@@ -0,0 +1,8 @@
+# K metadata for orangepi lts
+#  version 6.5 
+
+patch Input-axp20x-pek-allow-wakeup-after-shutdown-6_5.patch
+patch mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch
+patch mfd-Add-support-for-X-Powers-AC200.patch
+
+include orange-pi-3lts-common.scc

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/orange-pi-3lts-common.scc

@@ -0,0 +1,20 @@
+# Kmeta common
+#
+
+patch clk-Implement-protected-clocks-for-all-OF-clock-prov.patch
+patch Revert-clk-qcom-Support-protected-clocks-property.patch   
+patch rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch      
+patch firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch
+patch arm64-dts-allwinner-h6-Add-SCPI-protocol.patch   
+patch ASoC-hdmi-codec-fix-channel-allocation.patch               
+patch arm64-dts-h6-deinterlace.patch                               
+patch HACK-h6-Add-HDMI-sound-card.patch                            
+patch arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch    
+patch mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch   
+patch wip-fix-H6-4k-60.patch                                       
+patch arm64-dts-allwinner-h6-Fix-Cedrus-IOMMU-again.patch          
+patch iommu-sun50i-Allow-page-sizes-multiple-of-4096.patch 
+patch OrangePi-3-LTS-support.patch 
+patch arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch
+
+kconf harware orange-pi-3lts.cfg

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/orange-pi-3lts.cfg

@@ -0,0 +1,5 @@
+CONFIG_NVMEM_SUNXI_SID=y
+CONFIG_INIT_STACK_NONE=y
+CONFIG_PHY_SUN50I_USB3=y
+CONFIG_AC200_PHY=m
+CONFIG_MFD_AC200=m

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch

@@ -0,0 +1,62 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 2 Jan 2021 15:52:27 -0600
+Subject: [PATCH] rtc: sun6i: Allow RTC wakeup after shutdown
+
+Only IRQs that have enable_irq_wake() called on them can wake the system
+from sleep or after it has been shut down. Currently, the RTC alarm can
+only wake the system from sleep. Run the suspend callback to arm the IRQ
+during the shutdown process, so the RTC alarm also works after shutdown.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/rtc/rtc-sun6i.c | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+--- a/drivers/rtc/rtc-sun6i.c
++++ b/drivers/rtc/rtc-sun6i.c
+@@ -641,7 +641,6 @@ static const struct rtc_class_ops sun6i_
+ 	.alarm_irq_enable	= sun6i_rtc_alarm_irq_enable
+ };
+ 
+-#ifdef CONFIG_PM_SLEEP
+ /* Enable IRQ wake on suspend, to wake up from RTC. */
+ static int sun6i_rtc_suspend(struct device *dev)
+ {
+@@ -654,7 +653,7 @@ static int sun6i_rtc_suspend(struct devi
+ }
+ 
+ /* Disable IRQ wake on resume. */
+-static int sun6i_rtc_resume(struct device *dev)
++static int __maybe_unused sun6i_rtc_resume(struct device *dev)
+ {
+ 	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
+ 
+@@ -663,7 +662,6 @@ static int sun6i_rtc_resume(struct devic
+ 
+ 	return 0;
+ }
+-#endif
+ 
+ static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
+ 	sun6i_rtc_suspend, sun6i_rtc_resume);
+@@ -735,6 +733,11 @@ static int sun6i_rtc_probe(struct platfo
+ 	return 0;
+ }
+ 
++static void sun6i_rtc_shutdown(struct platform_device *pdev)
++{
++	sun6i_rtc_suspend(&pdev->dev);
++}
++
+ /*
+  * As far as RTC functionality goes, all models are the same. The
+  * datasheets claim that different models have different number of
+@@ -755,6 +758,7 @@ MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids
+ 
+ static struct platform_driver sun6i_rtc_driver = {
+ 	.probe		= sun6i_rtc_probe,
++	.shutdown	= sun6i_rtc_shutdown,
+ 	.driver		= {
+ 		.name		= "sun6i-rtc",
+ 		.of_match_table = sun6i_rtc_dt_ids,

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/orange-pi-3lts/wip-fix-H6-4k-60.patch

@@ -0,0 +1,75 @@
+From edc858b1d62ce5ffd8b8d10cc62425af15d48a91 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Wed, 8 Dec 2021 20:42:45 +0100
+Subject: [PATCH] wip: fix H6 4k@60
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 4 ++++
+ drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c    | 2 +-
+ 3 files changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index f08d0fded61f..bcd839a3ce80 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -1488,6 +1488,8 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
+ 	/* Override and disable clock termination. */
+ 	dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
+ 			      HDMI_3D_TX_PHY_CKCALCTRL);
++	if (mpixelclock == 594000000)
++		dw_hdmi_phy_i2c_write(hdmi, 0x8006, HDMI_3D_TX_PHY_MSM_CTRL);
+ 
+ 	return 0;
+ }
+@@ -2166,6 +2168,8 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi,
+ 	hdmi->hdmi_data.hdcp_enable = 0;
+ 	hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
+ 
++	hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP);
++
+ 	/* HDMI Initialization Step B.1 */
+ 	hdmi_av_composer(hdmi, &connector->display_info, mode);
+ 
+@@ -2205,6 +2209,9 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi,
+ 	hdmi_video_sample(hdmi);
+ 	hdmi_tx_hdcp_config(hdmi);
+ 
++	msleep(100);
++	hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP);
++
+ 	dw_hdmi_clear_overflow(hdmi);
+ 
+ 	return 0;
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
+index 1999db05bc3b..05182418efbb 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
+@@ -842,6 +842,10 @@ enum {
+ 	HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
+ 	HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
+ 
++/* HDMI_FC_GCP */
++	HDMI_FC_GCP_SET_AVMUTE = 0x2,
++	HDMI_FC_GCP_CLEAR_AVMUTE = 0x1,
++
+ /* FC_DBGFORCE field values */
+ 	HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
+ 	HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
+diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+index b64d93da651d..b70bc9de761f 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
++++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+@@ -90,7 +90,7 @@ static const struct dw_hdmi_mpll_config sun50i_h6_mpll_cfg[] = {
+ 		},
+ 	},  {
+ 		594000000, {
+-			{ 0x1a40, 0x0003 },
++			{ 0x1a7c, 0x0003 },
+ 			{ 0x3b4c, 0x0003 },
+ 			{ 0x5a64, 0x0003 },
+ 		},
+-- 
+2.34.1
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/0001-drv-fix-MAC-address-for-UWE5622.patch

@@ -0,0 +1,610 @@
+From 5e8062c5f6500526633934006c2858812961f6f4 Mon Sep 17 00:00:00 2001
+From: OpenEmbedded <oe.patch@oe>
+Date: Wed, 22 May 2024 15:36:46 +0200
+Subject: [PATCH] drv fix MAC address for UWE5622
+
+---
+ drivers/misc/Kconfig                 |   1 +
+ drivers/misc/Makefile                |   1 +
+ drivers/misc/sunxi-addr/Kconfig      |   7 +
+ drivers/misc/sunxi-addr/Makefile     |   6 +
+ drivers/misc/sunxi-addr/sha256.c     | 178 +++++++++++++
+ drivers/misc/sunxi-addr/sunxi-addr.c | 358 +++++++++++++++++++++++++++
+ 6 files changed, 551 insertions(+)
+ create mode 100644 drivers/misc/sunxi-addr/Kconfig
+ create mode 100644 drivers/misc/sunxi-addr/Makefile
+ create mode 100644 drivers/misc/sunxi-addr/sha256.c
+ create mode 100644 drivers/misc/sunxi-addr/sunxi-addr.c
+
+diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
+index cadd4a820..605e4d2ba 100644
+--- a/drivers/misc/Kconfig
++++ b/drivers/misc/Kconfig
+@@ -579,4 +579,5 @@ source "drivers/misc/cardreader/Kconfig"
+ source "drivers/misc/uacce/Kconfig"
+ source "drivers/misc/pvpanic/Kconfig"
+ source "drivers/misc/mchp_pci1xxxx/Kconfig"
++source "drivers/misc/sunxi-addr/Kconfig"
+ endmenu
+diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
+index f2a4d1ff6..06e857d70 100644
+--- a/drivers/misc/Makefile
++++ b/drivers/misc/Makefile
+@@ -67,3 +67,4 @@ obj-$(CONFIG_TMR_MANAGER)      += xilinx_tmr_manager.o
+ obj-$(CONFIG_TMR_INJECT)	+= xilinx_tmr_inject.o
+ obj-$(CONFIG_TPS6594_ESM)	+= tps6594-esm.o
+ obj-$(CONFIG_TPS6594_PFSM)	+= tps6594-pfsm.o
++obj-$(CONFIG_SUNXI_ADDR_MGT)    += sunxi-addr/
+diff --git a/drivers/misc/sunxi-addr/Kconfig b/drivers/misc/sunxi-addr/Kconfig
+new file mode 100644
+index 000000000..d7d0ca3bd
+--- /dev/null
++++ b/drivers/misc/sunxi-addr/Kconfig
+@@ -0,0 +1,7 @@
++config SUNXI_ADDR_MGT
++  tristate "Allwinner Network MAC Addess Manager"
++  depends on BT || ETHERNET || WLAN
++  depends on NVMEM_SUNXI_SID
++  help
++    allwinner network mac address management
++
+diff --git a/drivers/misc/sunxi-addr/Makefile b/drivers/misc/sunxi-addr/Makefile
+new file mode 100644
+index 000000000..9bafcece5
+--- /dev/null
++++ b/drivers/misc/sunxi-addr/Makefile
+@@ -0,0 +1,6 @@
++#
++# Makefile for wifi mac addr manager drivers
++#
++sunxi_addr-objs := sunxi-addr.o sha256.o
++obj-$(CONFIG_SUNXI_ADDR_MGT)   += sunxi_addr.o
++
+diff --git a/drivers/misc/sunxi-addr/sha256.c b/drivers/misc/sunxi-addr/sha256.c
+new file mode 100644
+index 000000000..78825810c
+--- /dev/null
++++ b/drivers/misc/sunxi-addr/sha256.c
+@@ -0,0 +1,178 @@
++/*
++ * Local implement of sha256.
++ *
++ * Copyright (C) 2013 Allwinner.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++#include <linux/kernel.h>
++#include <linux/string.h>
++
++/****************************** MACROS ******************************/
++#define ROTRIGHT(a, b) (((a) >> (b)) | ((a) << (32 - (b))))
++#define CH(x, y, z)    (((x) & (y)) ^ (~(x) & (z)))
++#define MAJ(x, y, z)   (((x) & (y)) ^  ((x) & (z)) ^ ((y) & (z)))
++#define EP0(x)         (ROTRIGHT(x,  2) ^ ROTRIGHT(x, 13) ^ ROTRIGHT(x, 22))
++#define EP1(x)         (ROTRIGHT(x,  6) ^ ROTRIGHT(x, 11) ^ ROTRIGHT(x, 25))
++#define SIG0(x)        (ROTRIGHT(x,  7) ^ ROTRIGHT(x, 18) ^ ((x) >> 3))
++#define SIG1(x)        (ROTRIGHT(x, 17) ^ ROTRIGHT(x, 19) ^ ((x) >> 10))
++
++/**************************** VARIABLES *****************************/
++static const uint32_t k[64] = {
++	0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5,
++	0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5,
++	0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
++	0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174,
++	0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc,
++	0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da,
++	0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7,
++	0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967,
++	0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13,
++	0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85,
++	0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3,
++	0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070,
++	0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5,
++	0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3,
++	0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
++	0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
++};
++
++struct sha256_ctx {
++	uint8_t data[64];   /* current 512-bit chunk of message data, just like a buffer */
++	uint32_t datalen;   /* sign the data length of current chunk */
++	uint64_t bitlen;    /* the bit length of the total message */
++	uint32_t state[8];  /* store the middle state of hash abstract */
++};
++
++/*********************** FUNCTION DEFINITIONS ***********************/
++static void sha256_transform(struct sha256_ctx *ctx, const uint8_t *data)
++{
++	uint32_t a, b, c, d, e, f, g, h, i, j, t1, t2, m[64];
++
++	/* initialization */
++	for (i = 0, j = 0; i < 16; ++i, j += 4)
++		m[i] = (data[j] << 24) | (data[j + 1] << 16) |
++			(data[j + 2] << 8) | (data[j + 3]);
++	for ( ; i < 64; ++i)
++		m[i] = SIG1(m[i - 2]) + m[i - 7] + SIG0(m[i - 15]) + m[i - 16];
++
++	a = ctx->state[0];
++	b = ctx->state[1];
++	c = ctx->state[2];
++	d = ctx->state[3];
++	e = ctx->state[4];
++	f = ctx->state[5];
++	g = ctx->state[6];
++	h = ctx->state[7];
++
++	for (i = 0; i < 64; ++i) {
++		t1 = h + EP1(e) + CH(e, f, g) + k[i] + m[i];
++		t2 = EP0(a) + MAJ(a, b, c);
++		h = g;
++		g = f;
++		f = e;
++		e = d + t1;
++		d = c;
++		c = b;
++		b = a;
++		a = t1 + t2;
++	}
++
++	ctx->state[0] += a;
++	ctx->state[1] += b;
++	ctx->state[2] += c;
++	ctx->state[3] += d;
++	ctx->state[4] += e;
++	ctx->state[5] += f;
++	ctx->state[6] += g;
++	ctx->state[7] += h;
++}
++
++static void sha256_init(struct sha256_ctx *ctx)
++{
++	ctx->datalen = 0;
++	ctx->bitlen = 0;
++	ctx->state[0] = 0x6a09e667;
++	ctx->state[1] = 0xbb67ae85;
++	ctx->state[2] = 0x3c6ef372;
++	ctx->state[3] = 0xa54ff53a;
++	ctx->state[4] = 0x510e527f;
++	ctx->state[5] = 0x9b05688c;
++	ctx->state[6] = 0x1f83d9ab;
++	ctx->state[7] = 0x5be0cd19;
++}
++
++static void sha256_update(struct sha256_ctx *ctx, const uint8_t *data, size_t len)
++{
++	uint32_t i;
++
++	for (i = 0; i < len; ++i) {
++		ctx->data[ctx->datalen] = data[i];
++		ctx->datalen++;
++		if (ctx->datalen == 64) {
++			/* 64 byte = 512 bit  means the buffer ctx->data has
++			 * fully stored one chunk of message,
++			 * so do the sha256 hash map for the current chunk.
++			 */
++			sha256_transform(ctx, ctx->data);
++			ctx->bitlen += 512;
++			ctx->datalen = 0;
++		}
++	}
++}
++
++static void sha256_final(struct sha256_ctx *ctx, uint8_t *hash)
++{
++	uint32_t i;
++
++	i = ctx->datalen;
++
++	/* Pad whatever data is left in the buffer. */
++	if (ctx->datalen < 56) {
++		ctx->data[i++] = 0x80;  /* pad 10000000 = 0x80 */
++		while (i < 56)
++			ctx->data[i++] = 0x00;
++	} else {
++		ctx->data[i++] = 0x80;
++		while (i < 64)
++			ctx->data[i++] = 0x00;
++		sha256_transform(ctx, ctx->data);
++		memset(ctx->data, 0, 56);
++	}
++
++	/* Append to the padding the total message's length in bits and transform. */
++	ctx->bitlen += ctx->datalen * 8;
++	ctx->data[63] = ctx->bitlen;
++	ctx->data[62] = ctx->bitlen >> 8;
++	ctx->data[61] = ctx->bitlen >> 16;
++	ctx->data[60] = ctx->bitlen >> 24;
++	ctx->data[59] = ctx->bitlen >> 32;
++	ctx->data[58] = ctx->bitlen >> 40;
++	ctx->data[57] = ctx->bitlen >> 48;
++	ctx->data[56] = ctx->bitlen >> 56;
++	sha256_transform(ctx, ctx->data);
++
++	/* copying the final state to the output hash(use big endian). */
++	for (i = 0; i < 4; ++i) {
++		hash[i]      = (ctx->state[0] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 4]  = (ctx->state[1] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 8]  = (ctx->state[2] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 12] = (ctx->state[3] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 16] = (ctx->state[4] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 20] = (ctx->state[5] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 24] = (ctx->state[6] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 28] = (ctx->state[7] >> (24 - i * 8)) & 0x000000ff;
++	}
++}
++
++int hmac_sha256(const uint8_t *plaintext, ssize_t psize, uint8_t *output)
++{
++	struct sha256_ctx ctx;
++
++	sha256_init(&ctx);
++	sha256_update(&ctx, plaintext, psize);
++	sha256_final(&ctx, output);
++	return 0;
++}
+diff --git a/drivers/misc/sunxi-addr/sunxi-addr.c b/drivers/misc/sunxi-addr/sunxi-addr.c
+new file mode 100644
+index 000000000..3ba0a113f
+--- /dev/null
++++ b/drivers/misc/sunxi-addr/sunxi-addr.c
+@@ -0,0 +1,358 @@
++/*
++ * The driver of SUNXI NET MAC ADDR Manager.
++ *
++ * Copyright (C) 2013 Allwinner.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++#define DEBUG
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/miscdevice.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++
++#define ADDR_MGT_DBG(fmt, arg...) printk(KERN_DEBUG "[ADDR_MGT] %s: " fmt "\n",\
++				__func__, ## arg)
++#define ADDR_MGT_ERR(fmt, arg...) printk(KERN_ERR "[ADDR_MGT] %s: " fmt "\n",\
++				__func__, ## arg)
++
++#define MODULE_CUR_VERSION  "v1.0.9"
++
++#define MATCH_STR_LEN       20
++#define ADDR_VAL_LEN        6
++#define ADDR_STR_LEN        18
++#define ID_LEN              16
++#define HASH_LEN            32
++
++#define TYPE_ANY            0
++#define TYPE_BURN           1
++#define TYPE_IDGEN          2
++#define TYPE_USER           3
++#define TYPE_RAND           4
++
++#define ADDR_FMT_STR        0
++#define ADDR_FMT_VAL        1
++
++#define IS_TYPE_INVALID(x)  ((x < TYPE_ANY) || (x > TYPE_RAND))
++
++#define ADDR_CLASS_ATTR_ADD(name) \
++static ssize_t addr_##name##_show(const struct class *class, \
++		const struct class_attribute *attr, char *buffer) \
++{ \
++	char addr[ADDR_STR_LEN]; \
++	if (IS_TYPE_INVALID(get_addr_by_name(ADDR_FMT_STR, addr, #name))) \
++		return 0; \
++	return sprintf(buffer, "%.17s\n", addr); \
++} \
++static ssize_t addr_##name##_store(const struct class *class, \
++		const struct class_attribute *attr, \
++		const char *buffer, size_t count) \
++{ \
++	if (count != ADDR_STR_LEN) { \
++		ADDR_MGT_ERR("Length wrong."); \
++		return -EINVAL; \
++	} \
++	set_addr_by_name(TYPE_USER, ADDR_FMT_STR, buffer, #name); \
++	return count; \
++} \
++static CLASS_ATTR_RW(addr_##name);
++
++struct addr_mgt_info {
++	unsigned int type_def;
++	unsigned int type_cur;
++	unsigned int flag;
++	char *addr;
++	char *name;
++};
++
++static struct addr_mgt_info info[] = {
++	{TYPE_ANY, TYPE_ANY, 1, NULL, "wifi"},
++	{TYPE_ANY, TYPE_ANY, 0, NULL, "bt"  },
++	{TYPE_ANY, TYPE_ANY, 1, NULL, "eth" },
++};
++
++extern int hmac_sha256(const uint8_t *plaintext, ssize_t psize, uint8_t *output);
++extern int sunxi_get_soc_chipid(unsigned char *chipid);
++
++static int addr_parse(int fmt, const char *addr, int check)
++{
++	char val_buf[ADDR_VAL_LEN];
++	char cmp_buf[ADDR_VAL_LEN];
++	int  ret = ADDR_VAL_LEN;
++
++	if (fmt == ADDR_FMT_STR)
++		ret = sscanf(addr, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
++					&val_buf[0], &val_buf[1], &val_buf[2],
++					&val_buf[3], &val_buf[4], &val_buf[5]);
++	else
++		memcpy(val_buf, addr, ADDR_VAL_LEN);
++
++	if (ret != ADDR_VAL_LEN)
++		return -1;
++
++	if (check && (val_buf[0] & 0x3))
++		return -1;
++
++	memset(cmp_buf, 0x00, ADDR_VAL_LEN);
++	if (memcmp(val_buf, cmp_buf, ADDR_VAL_LEN) == 0)
++		return -1;
++
++	memset(cmp_buf, 0xFF, ADDR_VAL_LEN);
++	if (memcmp(val_buf, cmp_buf, ADDR_VAL_LEN) == 0)
++		return -1;
++
++	return 0;
++}
++
++static struct addr_mgt_info *addr_find_by_name(char *name)
++{
++	int i = 0;
++	for (i = 0; i < ARRAY_SIZE(info); i++) {
++		if (strcmp(info[i].name, name) == 0)
++			return &info[i];
++	}
++	return NULL;
++}
++
++static int get_addr_by_name(int fmt, char *addr, char *name)
++{
++	struct addr_mgt_info *t;
++
++	t = addr_find_by_name(name);
++	if (t == NULL) {
++		ADDR_MGT_ERR("can't find addr named: %s", name);
++		return -1;
++	}
++
++	if (IS_TYPE_INVALID(t->type_cur)) {
++		ADDR_MGT_ERR("addr type invalid");
++		return -1;
++	}
++
++	if (addr_parse(ADDR_FMT_VAL, t->addr, t->flag)) {
++		ADDR_MGT_ERR("addr parse fail(%s)", t->addr);
++		return -1;
++	}
++
++	if (fmt == ADDR_FMT_STR)
++		sprintf(addr, "%02X:%02X:%02X:%02X:%02X:%02X",
++				t->addr[0], t->addr[1], t->addr[2],
++				t->addr[3], t->addr[4], t->addr[5]);
++	else
++		memcpy(addr, t->addr, ADDR_VAL_LEN);
++
++	return t->type_cur;
++}
++
++static int set_addr_by_name(int type, int fmt, const char *addr, char *name)
++{
++	struct addr_mgt_info *t;
++
++	t = addr_find_by_name(name);
++	if (t == NULL) {
++		ADDR_MGT_ERR("can't find addr named: %s", name);
++		return -1;
++	}
++
++	if (addr_parse(fmt, addr, t->flag)) {
++		ADDR_MGT_ERR("addr parse fail(%s)", addr);
++		return -1;
++	}
++
++	t->type_cur = type;
++	if (fmt == ADDR_FMT_STR)
++		sscanf(addr, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
++				&t->addr[0], &t->addr[1], &t->addr[2],
++				&t->addr[3], &t->addr[4], &t->addr[5]);
++	else
++		memcpy(t->addr, addr, ADDR_VAL_LEN);
++
++	return 0;
++}
++
++int get_custom_mac_address(int fmt, char *name, char *addr)
++{
++	return get_addr_by_name(fmt, addr, name);
++}
++EXPORT_SYMBOL_GPL(get_custom_mac_address);
++
++static int addr_factory(struct device_node *np,
++			int idx, int type, char *mac, char *name)
++{
++	int  ret, i;
++	char match[MATCH_STR_LEN];
++	const char *p;
++	char id[ID_LEN], hash[HASH_LEN], cmp_buf[ID_LEN];
++	struct timespec64 curtime;
++
++	switch (type) {
++	case TYPE_BURN:
++		sprintf(match, "addr_%s", name);
++		ret = of_property_read_string_index(np, match, 0, &p);
++		if (ret)
++			return -1;
++
++		ret = sscanf(p, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
++			&mac[0], &mac[1], &mac[2],
++			&mac[3], &mac[4], &mac[5]);
++
++		if (ret != ADDR_VAL_LEN)
++			return -1;
++		break;
++	case TYPE_IDGEN:
++		if (idx > HASH_LEN / ADDR_VAL_LEN - 1)
++			return -1;
++		if (sunxi_get_soc_chipid(id))
++			return -1;
++		memset(cmp_buf, 0x00, ID_LEN);
++		if (memcmp(id, cmp_buf, ID_LEN) == 0)
++			return -1;
++		if (hmac_sha256(id, ID_LEN, hash))
++			return -1;
++		memcpy(mac, &hash[idx * ADDR_VAL_LEN], ADDR_VAL_LEN);
++		break;
++	case TYPE_RAND:
++		for (i = 0; i < ADDR_VAL_LEN; i++) {
++			ktime_get_real_ts64(&curtime);
++			mac[i] = (char)curtime.tv_nsec;
++		}
++		break;
++	default:
++		ADDR_MGT_ERR("unsupport type: %d", type);
++		return -1;
++	}
++	return 0;
++}
++
++static int addr_init(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	int  type, i, j;
++	char match[MATCH_STR_LEN];
++	char addr[ADDR_VAL_LEN];
++	int  type_tab[] = {TYPE_BURN, TYPE_IDGEN, TYPE_RAND};
++
++	/* init addr type and value */
++	for (i = 0; i < ARRAY_SIZE(info); i++) {
++		sprintf(match, "type_addr_%s", info[i].name);
++		if (of_property_read_u32(np, match, &type)) {
++			ADDR_MGT_DBG("Failed to get type_def_%s, use default: %d",
++						info[i].name, info[i].type_def);
++		} else {
++			info[i].type_def = type;
++			info[i].type_cur = type;
++		}
++
++		if (IS_TYPE_INVALID(info[i].type_def))
++			return -1;
++		if (info[i].type_def != TYPE_ANY) {
++			if (addr_factory(np, i, info[i].type_def, addr, info[i].name))
++				return -1;
++		} else {
++			for (j = 0; j < ARRAY_SIZE(type_tab); j++) {
++				if (!addr_factory(np, i, type_tab[j], addr, info[i].name)) {
++					info[i].type_cur = type_tab[j];
++					break;
++				}
++			}
++		}
++
++		if (info[i].flag)
++			addr[0] &= 0xFC;
++
++		if (addr_parse(ADDR_FMT_VAL, addr, info[i].flag))
++			return -1;
++		else {
++			info[i].addr = devm_kzalloc(&pdev->dev, ADDR_VAL_LEN, GFP_KERNEL);
++			memcpy(info[i].addr, addr, ADDR_VAL_LEN);
++		}
++	}
++	return 0;
++}
++
++static ssize_t summary_show(const struct class *class,
++				const struct class_attribute *attr, char *buffer)
++{
++	int i = 0, ret = 0;
++
++	ret += sprintf(&buffer[ret], "name cfg cur address\n");
++	for (i = 0; i < ARRAY_SIZE(info); i++) {
++		ret += sprintf(&buffer[ret],
++			"%4s  %d   %d  %02X:%02X:%02X:%02X:%02X:%02X\n",
++			info[i].name,   info[i].type_def, info[i].type_cur,
++			info[i].addr[0], info[i].addr[1], info[i].addr[2],
++			info[i].addr[3], info[i].addr[4], info[i].addr[5]);
++	}
++	return ret;
++}
++static CLASS_ATTR_RO(summary);
++
++ADDR_CLASS_ATTR_ADD(wifi);
++ADDR_CLASS_ATTR_ADD(bt);
++ADDR_CLASS_ATTR_ADD(eth);
++
++static struct attribute *addr_class_attrs[] = {
++	&class_attr_summary.attr,
++	&class_attr_addr_wifi.attr,
++	&class_attr_addr_bt.attr,
++	&class_attr_addr_eth.attr,
++	NULL
++};
++ATTRIBUTE_GROUPS(addr_class);
++
++static struct class addr_class = {
++	.name = "addr_mgt",
++	.class_groups = addr_class_groups,
++};
++
++static const struct of_device_id addr_mgt_ids[] = {
++	{ .compatible = "allwinner,sunxi-addr_mgt" },
++	{ /* Sentinel */ }
++};
++
++static int addr_mgt_probe(struct platform_device *pdev)
++{
++	int status;
++
++	ADDR_MGT_DBG("module version: %s", MODULE_CUR_VERSION);
++	status = class_register(&addr_class);
++	if (status < 0) {
++		ADDR_MGT_ERR("class register error, status: %d.", status);
++		return -1;
++	}
++
++	if (addr_init(pdev)) {
++		ADDR_MGT_ERR("failed to init addr.");
++		class_unregister(&addr_class);
++		return -1;
++	}
++	ADDR_MGT_DBG("success.");
++	return 0;
++}
++
++static int addr_mgt_remove(struct platform_device *pdev)
++{
++	class_unregister(&addr_class);
++	return 0;
++}
++
++static struct platform_driver addr_mgt_driver = {
++	.probe  = addr_mgt_probe,
++	.remove = addr_mgt_remove,
++	.driver = {
++		.owner = THIS_MODULE,
++		.name  = "sunxi-addr-mgt",
++		.of_match_table = addr_mgt_ids,
++	},
++};
++
++module_platform_driver_probe(addr_mgt_driver, addr_mgt_probe);
++
++MODULE_AUTHOR("Allwinnertech");
++MODULE_DESCRIPTION("Network MAC Addess Manager");
++MODULE_LICENSE("GPL");
++

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/add-uwe5622-to-wireless-makefile.patch

@@ -0,0 +1,25 @@
+From e5017f74e32f644f9c707f788b2aaf47a98b820c Mon Sep 17 00:00:00 2001
+From: OpenEmbedded <oe.patch@oe>
+Date: Wed, 6 Dec 2023 00:38:22 +0100
+Subject: [PATCH 2/2] add uwe5622 to wireless makefile
+
+---
+ drivers/net/wireless/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
+index a61cf6c90..455cf9296 100644
+--- a/drivers/net/wireless/Makefile
++++ b/drivers/net/wireless/Makefile
+@@ -2,7 +2,7 @@
+ #
+ # Makefile for the Linux Wireless network device drivers.
+ #
+-
++obj-$(CONFIG_SPARD_WLAN_SUPPORT) += uwe5622/
+ obj-$(CONFIG_WLAN_VENDOR_ADMTEK) += admtek/
+ obj-$(CONFIG_WLAN_VENDOR_ATH) += ath/
+ obj-$(CONFIG_WLAN_VENDOR_ATMEL) += atmel/
+-- 
+2.43.0
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/fix-makefiles-for-yocto-build.patch

@@ -0,0 +1,50 @@
+From 3c57b45edef027fe994cd469185f10a04f12dcd7 Mon Sep 17 00:00:00 2001
+From: OpenEmbedded <oe.patch@oe>
+Date: Sat, 25 Nov 2023 14:39:37 +0000
+Subject: [PATCH] fix makefiles for yocto build
+
+---
+ drivers/net/wireless/uwe5622/Makefile           | 2 +-
+ drivers/net/wireless/uwe5622/unisocwcn/Makefile | 9 +++++----
+ 2 files changed, 6 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/wireless/uwe5622/Makefile b/drivers/net/wireless/uwe5622/Makefile
+index d2210439f3cc..09e06defdfcf 100644
+--- a/drivers/net/wireless/uwe5622/Makefile
++++ b/drivers/net/wireless/uwe5622/Makefile
+@@ -2,7 +2,7 @@ obj-$(CONFIG_RK_WIFI_DEVICE_UWE5622) += unisocwcn/
+ obj-$(CONFIG_WLAN_UWE5622)    += unisocwifi/
+ obj-$(CONFIG_TTY_OVERY_SDIO)  += tty-sdio/
+ 
+-UNISOCWCN_DIR := $(shell cd $(src)/unisocwcn/ && /bin/pwd)
++UNISOCWCN_DIR := $(dir $(realpath $(lastword $(MAKEFILE_LIST))))unisocwcn
+ UNISOC_BSP_INCLUDE := $(UNISOCWCN_DIR)/include
+ export UNISOC_BSP_INCLUDE
+ 
+diff --git a/drivers/net/wireless/uwe5622/unisocwcn/Makefile b/drivers/net/wireless/uwe5622/unisocwcn/Makefile
+index 939acb5c9274..a582426995ed 100755
+--- a/drivers/net/wireless/uwe5622/unisocwcn/Makefile
++++ b/drivers/net/wireless/uwe5622/unisocwcn/Makefile
+@@ -129,9 +129,10 @@ ccflags-y += -DCONFIG_WCN_BOOT
+ ccflags-y += -DCONFIG_WCN_UTILS
+ 
+ #### include path ######
+-ccflags-y += -I$(src)/include/
+-ccflags-y += -I$(src)/platform/
+-ccflags-y += -I$(src)/platform/rf/
++local_src__ := $(dir $(realpath $(lastword $(MAKEFILE_LIST))))
++ccflags-y += -I$(local_src__)include/
++ccflags-y += -I$(local_src__)platform/
++ccflags-y += -I$(local_src__)platform/rf/
+ 
+ #### add cflag for Customer ######
+ ### ---------- Hisilicon start ---------- ###
+@@ -405,7 +406,7 @@ KDIR ?= $(ANDROID_PRODUCT_OUT)/obj/KERNEL_OBJ
+ ARCH ?= arm
+ CROSS_COMPILE ?= arm-histbv310-linux-
+ 
+-EXTRA_CFLAGS += -I$(src)/include -D__linux__
++EXTRA_CFLAGS += -I$(local_src__)include -D__linux__
+ 
+ all: $(all_dependencies)
+ 

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/uwe5622-6_1.scc

@@ -0,0 +1,10 @@
+
+# Kmeta for uwe5622
+# for 6.1 kernel
+# source: armbian misc drivers
+
+
+patch uwe5622-allwinner.patch 
+patch uwe5622-allwinner-bugfix.patch 
+
+include uwe5622-common.scc

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/uwe5622-6_5.scc

@@ -0,0 +1,11 @@
+# Kmeta for uwe5622
+# patches for 6.5 & 6.6
+
+
+patch uwe5622-allwinner-v6.3.patch
+patch uwe5622-allwinner-bugfix-v6.3.patch
+patch uwe5622-allwinner-v6.3-compilation-fix.patch
+patch uwe5622-v6.4-post.patch
+
+include uwe5622-common.scc
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/uwe5622-6_6.scc

@@ -0,0 +1,9 @@
+# Kmeta for uwe5622
+# for kernel 6.6 only
+
+include uwe5622-6_5.scc
+
+patch uwe5622-v6.6-fix-tty-sdio.patch
+
+# Add driver for MAC address fix
+patch 0001-drv-fix-MAC-address-for-UWE5622.patch

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/uwe5622-6_7.scc

@@ -0,0 +1,7 @@
+# Kmeta for uwe5622
+# for kernel 6.7 
+# simply includes 6.6 metadata
+
+include uwe5622-6_6.scc
+
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/uwe5622-allwinner-v6.3-compilation-fix.patch

@@ -0,0 +1,47 @@
+From 9a649d7ad384907ba8f62ba50a6fd7e524d8ce25 Mon Sep 17 00:00:00 2001
+From: root <Gunjan Gupta>
+Date: Sun, 17 Sep 2023 20:45:44 +0000
+Subject: [PATCH] drivers: uwe5622: fix compilation on 6.3+ kernels
+
+---
+ .../wireless/uwe5622/unisocwcn/platform/wcn_boot.c    | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_boot.c b/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_boot.c
+index 220bac67ddd0..b243b39c2133 100644
+--- a/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_boot.c
++++ b/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_boot.c
+@@ -1371,15 +1371,13 @@ static int marlin_registsr_bt_wake(struct device *dev)
+ {
+ 	struct device_node *np;
+ 	int bt_wake_host_gpio, ret = 0;
+-	struct gpio_config config;
+ 
+ 	np = of_find_compatible_node(NULL, NULL, "allwinner,sunxi-btlpm");
+ 	if (!np) {
+ 		WCN_ERR("dts node for bt_wake not found");
+ 		return -EINVAL;
+ 	}
+-	bt_wake_host_gpio = of_get_named_gpio_flags(np, "bt_hostwake", 0,
+-		(enum of_gpio_flags *)&config);
++	bt_wake_host_gpio = of_get_named_gpio(np, "bt_hostwake", 0);
+ 	if (!gpio_is_valid(bt_wake_host_gpio)) {
+ 		WCN_ERR("bt_hostwake irq is invalid: %d\n",
+ 			bt_wake_host_gpio);
+@@ -1403,11 +1401,8 @@ static int marlin_registsr_bt_wake(struct device *dev)
+ 
+ 	marlin_dev->bt_wake_host_int_num = gpio_to_irq(bt_wake_host_gpio);
+ 
+-	WCN_INFO("%s bt_hostwake gpio=%d mul-sel=%d pull=%d "
+-		 "drv_level=%d data=%d intnum=%d\n",
+-		 __func__, config.gpio, config.mul_sel, config.pull,
+-		 config.drv_level, config.data,
+-		 marlin_dev->bt_wake_host_int_num);
++	WCN_INFO("%s bt_hostwake gpio=%d intnum=%d\n", __func__,
++		 bt_wake_host_gpio, marlin_dev->bt_wake_host_int_num);
+ 
+ 	ret = device_init_wakeup(dev, true);
+ 	if (ret < 0) {
+-- 
+2.34.1
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/uwe5622-common.scc

@@ -0,0 +1,18 @@
+# Kmeta for uwe5622
+# common patches for kernel versions 6.1, 6.5, 6.6 & 6.7
+# source: armbian misc drivers
+
+# common patches to be appliend after kernel version specific ones
+
+patch uwe5622-warnings.patch
+patch uwe5622-park-link-v6.1-post.patch
+patch uwe5622-v6.1.patch
+patch uwe5622-fix-setting-mac-address-for-netdev.patch
+patch wireless-uwe5622-Fix-compilation-with-6.7-kernel.patch
+patch wireless-uwe5622-reduce-system-load.patch
+
+# Custom: Add driver to makefile and patch Makefiles to make it work with yocto.
+patch add-uwe5622-to-wireless-makefile.patch
+patch fix-makefiles-for-yocto-build.patch
+
+kconf harware uwe5622-fragment.cfg

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/uwe5622-fix-setting-mac-address-for-netdev.patch

@@ -0,0 +1,35 @@
+From 9211a92d07e9a43fce104f87f9d45e890257b699 Mon Sep 17 00:00:00 2001
+From: pbiel <pbiel7@gmail.com>
+Date: Tue, 7 Mar 2023 20:28:44 +0100
+Subject: [PATCH] wireless: fix setting mac address for netdev in uwe5622
+ unisocwifi driver
+
+---
+ drivers/net/wireless/uwe5622/unisocwifi/main.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/uwe5622/unisocwifi/main.c b/drivers/net/wireless/uwe5622/unisocwifi/main.c
+index 21efdf4e0..566a9a7f3 100644
+--- a/drivers/net/wireless/uwe5622/unisocwifi/main.c
++++ b/drivers/net/wireless/uwe5622/unisocwifi/main.c
+@@ -1356,6 +1356,7 @@ static struct sprdwl_vif *sprdwl_register_netdev(struct sprdwl_priv *priv,
+ 	struct wireless_dev *wdev;
+ 	struct sprdwl_vif *vif;
+ 	int ret;
++	u8 target_mac_addr[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+ 
+ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0))
+ 	ndev = alloc_netdev(sizeof(*vif), name, NET_NAME_UNKNOWN, ether_setup);
+@@ -1411,7 +1412,8 @@ static struct sprdwl_vif *sprdwl_register_netdev(struct sprdwl_priv *priv,
+ 	ndev->features |= NETIF_F_SG;
+ 	SET_NETDEV_DEV(ndev, wiphy_dev(priv->wiphy));
+ 
+-	sprdwl_set_mac_addr(vif, addr, ndev->dev_addr);
++	sprdwl_set_mac_addr(vif, addr, target_mac_addr);
++	dev_addr_set(ndev, target_mac_addr);
+ 
+ #ifdef CONFIG_P2P_INTF
+ 	if (type == NL80211_IFTYPE_P2P_DEVICE)
+-- 
+2.34.1
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/uwe5622-fragment.cfg

@@ -0,0 +1,11 @@
+CONFIG_SPARD_WLAN_SUPPORT=y
+CONFIG_WCN_BSP_DRIVER_BUILDIN=y
+CONFIG_WLAN_UWE5621=m
+CONFIG_WLAN_UWE5622=m
+CONFIG_SPRDWL_NG=m
+CONFIG_UNISOC_WIFI_PS=y
+CONFIG_TTY_OVERY_SDIO=m
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_LIB_SHA256=y
+
+CONFIG_NVMEM_SUNXI_SID=m

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/uwe5622-park-link-v6.1-post.patch

@@ -0,0 +1,58 @@
+From 67b790ecbeab3f5493dc8306e87e503e1bb7bcdc Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 29 Jan 2023 13:43:27 +0000
+Subject: [PATCH] fix spreadtrum (sprd) bluetooth broken park link status
+
+---
+ drivers/bluetooth/hci_ldisc.c | 6 ++++++
+ include/net/bluetooth/hci.h   | 6 ++++++
+ net/bluetooth/hci_sync.c      | 2 +-
+ 3 files changed, 13 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/bluetooth/hci_ldisc.c b/drivers/bluetooth/hci_ldisc.c
+--- a/drivers/bluetooth/hci_ldisc.c	(revision 58aa050aa57333b34b358234002121c59fb3af26)
++++ b/drivers/bluetooth/hci_ldisc.c	(revision bf8ab2f58b21494ffde96979431a3da931deb48b)
+@@ -658,6 +658,12 @@
+ 	hdev->setup = hci_uart_setup;
+ 	SET_HCIDEV_DEV(hdev, hu->tty->dev);
+ 
++	// Set the broken Park link status quirk, specific for spreadtrum (sprd)
++	// bluetooth devices
++	if (hdev->manufacturer == 0xffff && hu->tty->driver &&
++		strncmp(hu->tty->driver->name, "ttyBT", 5) == 0)
++		set_bit(HCI_QUIRK_BROKEN_PARK_LINK_STATUS, &hdev->quirks);
++
+ 	if (test_bit(HCI_UART_RAW_DEVICE, &hu->hdev_flags))
+ 		set_bit(HCI_QUIRK_RAW_DEVICE, &hdev->quirks);
+ 
+diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h
+--- a/include/net/bluetooth/hci.h	(revision 58aa050aa57333b34b358234002121c59fb3af26)
++++ b/include/net/bluetooth/hci.h	(revision bf8ab2f58b21494ffde96979431a3da931deb48b)
+@@ -309,6 +309,12 @@
+ 
+ /* HCI device quirks */
+ enum {
++	/*
++	 * Device declares that support Park link status, but it really
++	 * does not support it and fails to initialize
++	 */
++	HCI_QUIRK_BROKEN_PARK_LINK_STATUS,
++
+ 	/* When this quirk is set, the HCI Reset command is send when
+ 	 * closing the transport instead of when opening it.
+ 	 *
+diff --git a/net/bluetooth/hci_sync.c b/net/bluetooth/hci_sync.c
+--- a/net/bluetooth/hci_sync.c	(revision 58aa050aa57333b34b358234002121c59fb3af26)
++++ b/net/bluetooth/hci_sync.c	(revision bf8ab2f58b21494ffde96979431a3da931deb48b)
+@@ -3804,7 +3804,7 @@
+ 		link_policy |= HCI_LP_HOLD;
+ 	if (lmp_sniff_capable(hdev))
+ 		link_policy |= HCI_LP_SNIFF;
+-	if (lmp_park_capable(hdev))
++	if (lmp_park_capable(hdev) && !test_bit(HCI_QUIRK_BROKEN_PARK_LINK_STATUS, &hdev->quirks))
+ 		link_policy |= HCI_LP_PARK;
+ 
+ 	cp.policy = cpu_to_le16(link_policy);
+-- 
+2.34.1
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/uwe5622-v6.1.patch

@@ -0,0 +1,65 @@
+From 7c0e3b529afd31f99baf78be10b5d71d9086789a Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 29 Jan 2023 15:53:20 +0000
+Subject: [PATCH] port uwe5622 driver to kernel 6.1
+
+---
+ drivers/net/wireless/uwe5622/unisocwifi/cfg80211.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/wireless/uwe5622/unisocwifi/cfg80211.c b/drivers/net/wireless/uwe5622/unisocwifi/cfg80211.c
+index 294f19e1f6c..9dcdee02cb9 100755
+--- a/drivers/net/wireless/uwe5622/unisocwifi/cfg80211.c
++++ b/drivers/net/wireless/uwe5622/unisocwifi/cfg80211.c
+@@ -703,7 +703,7 @@ static int sprdwl_add_cipher_key(struct sprdwl_vif *vif, bool pairwise,
+ }
+ 
+ static int sprdwl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev,
+-				   u8 key_index, bool pairwise,
++				   int link_id, u8 key_index, bool pairwise,
+ 				   const u8 *mac_addr,
+ 				   struct key_params *params)
+ {
+@@ -725,7 +725,7 @@ static int sprdwl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev,
+ }
+ 
+ static int sprdwl_cfg80211_del_key(struct wiphy *wiphy, struct net_device *ndev,
+-				   u8 key_index, bool pairwise,
++				   int link_id, u8 key_index, bool pairwise,
+ 				   const u8 *mac_addr)
+ {
+ 	struct sprdwl_vif *vif = netdev_priv(ndev);
+@@ -755,7 +755,7 @@ static int sprdwl_cfg80211_del_key(struct wiphy *wiphy, struct net_device *ndev,
+ 
+ static int sprdwl_cfg80211_set_default_key(struct wiphy *wiphy,
+ 					   struct net_device *ndev,
+-					   u8 key_index, bool unicast,
++					   int link_id, u8 key_index, bool unicast,
+ 					   bool multicast)
+ {
+ 	struct sprdwl_vif *vif = netdev_priv(ndev);
+@@ -2383,7 +2383,7 @@ void sprdwl_report_connection(struct sprdwl_vif *vif,
+ 		 conn_info->status == SPRDWL_ROAM_SUCCESS){
+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
+ 		struct cfg80211_roam_info roam_info = {
+-			.bss = bss,
++			.links[0].bss = bss,
+ 			.req_ie = conn_info->req_ie,
+ 			.req_ie_len = conn_info->req_ie_len,
+ 			.resp_ie = conn_info->resp_ie,
+-- 
+2.34.1
+
+diff --git a/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_parn_parser.c b/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_parn_parser.c
+index 0aa765ad839..20aea5e7366 100644
+--- a/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_parn_parser.c
++++ b/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_parn_parser.c
+@@ -143,7 +143,7 @@ static int prefixcmp(const char *str, const char *prefix)
+ }
+ 
+ #if KERNEL_VERSION(3, 19, 0) <= LINUX_VERSION_CODE
+-static int find_callback(struct dir_context *ctx, const char *name, int namlen,
++static bool find_callback(struct dir_context *ctx, const char *name, int namlen,
+ 		     loff_t offset, u64 ino, unsigned int d_type)
+ #else
+ static int find_callback(void *ctx, const char *name, int namlen,

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/uwe5622-v6.4-post.patch

@@ -0,0 +1,34 @@
+From 5b43103009736d5efff606ca40a1a693ba8a04c2 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Thu, 3 Aug 2023 10:09:46 +0200
+Subject: [PATCH] fix driver for kernel 6.4
+
+---
+ drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_log.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_log.c b/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_log.c
+index 1a78b5b035a4..c68d86a20fe2 100644
+--- a/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_log.c
++++ b/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_log.c
+@@ -260,7 +260,7 @@ int log_cdev_init(void)
+ 	struct wcnlog_dev *dev[WCN_LOG_MAX_MINOR] = {NULL};
+ 
+ 	WCN_DEBUG("log_cdev_init\n");
+-	wcnlog_class = class_create(THIS_MODULE, "slog_wcn");
++	wcnlog_class = class_create("slog_wcn");
+ 	if (IS_ERR(wcnlog_class))
+ 		return PTR_ERR(wcnlog_class);
+ 
+diff --git a/drivers/net/wireless/uwe5622/tty-sdio/lpm.c b/drivers/net/wireless/uwe5622/tty-sdio/lpm.c
+index 1570676ced50..79a6d60c94e8 100644
+--- a/drivers/net/wireless/uwe5622/tty-sdio/lpm.c
++++ b/drivers/net/wireless/uwe5622/tty-sdio/lpm.c
+@@ -11,6 +11,7 @@
+ #include <linux/seq_file.h>
+ #include <linux/version.h>
+ #include <linux/export.h>
++#include <linux/device.h>
+ #include <marlin_platform.h>
+ 
+ #define VERSION         "marlin2 V0.1"

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/uwe5622-v6.6-fix-tty-sdio.patch

@@ -0,0 +1,27 @@
+From 332748a389a88f8d78c5b2c70cf5c29f7098c703 Mon Sep 17 00:00:00 2001
+From: Ricardo Pardini <ricardo@pardini.net>
+Date: Mon, 2 Oct 2023 16:24:12 +0200
+Subject: [PATCH] wifi uwe fix uwe5622 tty-sdio
+
+---
+ drivers/net/wireless/uwe5622/tty-sdio/tty.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/wireless/uwe5622/tty-sdio/tty.c b/drivers/net/wireless/uwe5622/tty-sdio/tty.c
+index 6498272fc192..36fc7dd558d4 100644
+--- a/drivers/net/wireless/uwe5622/tty-sdio/tty.c
++++ b/drivers/net/wireless/uwe5622/tty-sdio/tty.c
+@@ -467,8 +467,8 @@ static  int sdio_data_transmit(uint8_t *data, size_t count)
+ 	return mtty_write(NULL, data, count);
+ }
+ 
+-static int mtty_write_plus(struct tty_struct *tty,
+-		  const unsigned char *buf, int count)
++static ssize_t mtty_write_plus(struct tty_struct *tty, const u8 *buf,
++			     size_t count)
+ {
+ 	return sitm_write(buf, count, sdio_data_transmit);
+ }
+-- 
+2.42.0
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/uwe5622-warnings.patch

@@ -0,0 +1,206 @@
+From b758478655da935b50a973b0aa2ddbc20893b789 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 12 Jun 2022 14:33:59 +0000
+Subject: [PATCH] uwe5622: various warning and firmware path fixes
+
+---
+ drivers/net/wireless/uwe5622/Makefile         |  2 +-
+ .../uwe5622/unisocwcn/platform/rdc_debug.c    |  4 +-
+ .../uwe5622/unisocwcn/platform/wcn_boot.c     |  2 -
+ .../unisocwcn/platform/wcn_parn_parser.c      |  2 +-
+ .../uwe5622/unisocwcn/sdio/sdiohal_ctl.c      | 42 ++++++-------------
+ .../wireless/uwe5622/unisocwifi/cfg80211.c    |  4 --
+ 6 files changed, 17 insertions(+), 39 deletions(-)
+
+diff --git a/drivers/net/wireless/uwe5622/Makefile b/drivers/net/wireless/uwe5622/Makefile
+index 71c863c1017..d2210439f3c 100644
+--- a/drivers/net/wireless/uwe5622/Makefile
++++ b/drivers/net/wireless/uwe5622/Makefile
+@@ -6,5 +6,5 @@ UNISOCWCN_DIR := $(shell cd $(src)/unisocwcn/ && /bin/pwd)
+ UNISOC_BSP_INCLUDE := $(UNISOCWCN_DIR)/include
+ export UNISOC_BSP_INCLUDE
+ 
+-UNISOC_FW_PATH_CONFIG := "/lib/firmware/"
++UNISOC_FW_PATH_CONFIG := "/lib/firmware/uwe5622/"
+ export UNISOC_FW_PATH_CONFIG
+diff --git a/drivers/net/wireless/uwe5622/unisocwcn/platform/rdc_debug.c b/drivers/net/wireless/uwe5622/unisocwcn/platform/rdc_debug.c
+index 86fa3b103ad..1343cb98362 100755
+--- a/drivers/net/wireless/uwe5622/unisocwcn/platform/rdc_debug.c
++++ b/drivers/net/wireless/uwe5622/unisocwcn/platform/rdc_debug.c
+@@ -41,13 +41,13 @@ static unsigned int wcn_cp2_file_max_num = UNISOC_DBG_FILENUM_DEFAULT;
+  */
+ static unsigned int wcn_cp2_log_cover_old = 1;
+ /* path of config file unisoc_cp2log_config.txt */
+-#define WCN_DEBUG_CFG_MAX_PATH_NUM	0
++#define WCN_DEBUG_CFG_MAX_PATH_NUM	2
+ static char *wcn_cp2_config_path[WCN_DEBUG_CFG_MAX_PATH_NUM] = {
+ 	"/data/unisoc_cp2log_config.txt",
+ 	"/vendor/etc/wifi/unisoc_cp2log_config.txt"
+ };
+ /* path of cp2 log and mem files. */
+-#define WCN_UNISOC_DBG_MAX_PATH_NUM	0
++#define WCN_UNISOC_DBG_MAX_PATH_NUM	3
+ static char *wcn_unisoc_dbg_path[WCN_UNISOC_DBG_MAX_PATH_NUM] = {
+ 	UNISOC_DBG_PATH_DEFAULT,/* most of projects */
+ 	"/data",		/* amlogic s905w... */
+diff --git a/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_boot.c b/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_boot.c
+index d82f56357f3..58b9d290f23 100755
+--- a/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_boot.c
++++ b/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_boot.c
+@@ -325,8 +325,6 @@ static struct regmap *reg_map;
+ #define AFC_CALI_READ_FINISH 0x12121212
+ #define WCN_AFC_CALI_PATH "/productinfo/wcn/tsx_bt_data.txt"
+ 
+-#define BIT(nr) (1UL << (nr))
+-
+ #ifdef CONFIG_WCN_DOWNLOAD_FIRMWARE_FROM_HEX
+ #define POWER_WQ_DELAYED_MS 0
+ #else
+diff --git a/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_parn_parser.c b/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_parn_parser.c
+index 9abcd326972..c1557dcce3f 100755
+--- a/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_parn_parser.c
++++ b/drivers/net/wireless/uwe5622/unisocwcn/platform/wcn_parn_parser.c
+@@ -183,7 +183,7 @@ int parse_firmware_path(char *firmware_path)
+ 			continue;
+ 		}
+ 		memset(fstab_name, 0, sizeof(fstab_name));
+-		strncpy(fstab_name, fstab_dir[loop], sizeof(fstab_dir[loop]));
++		strncpy(fstab_name, fstab_dir[loop], sizeof(fstab_name));
+ 		if (strlen(fstab_name) > 1)
+ 			fstab_name[strlen(fstab_name)] = '/';
+ 		iterate_dir(file1, &ctx);
+diff --git a/drivers/net/wireless/uwe5622/unisocwcn/sdio/sdiohal_ctl.c b/drivers/net/wireless/uwe5622/unisocwcn/sdio/sdiohal_ctl.c
+index b426bf89cd9..8000bfea378 100755
+--- a/drivers/net/wireless/uwe5622/unisocwcn/sdio/sdiohal_ctl.c
++++ b/drivers/net/wireless/uwe5622/unisocwcn/sdio/sdiohal_ctl.c
+@@ -9,6 +9,7 @@
+ #include <linux/uaccess.h>
+ #include <linux/version.h>
+ #include <linux/vmalloc.h>
++#include <linux/ktime.h>
+ #include <wcn_bus.h>
+ 
+ #include "sdiohal.h"
+@@ -96,8 +97,10 @@ char *tp_tx_buf[TP_TX_BUF_CNT];
+ 
+ struct mchn_ops_t at_tx_ops;
+ struct mchn_ops_t at_rx_ops;
+-struct timeval tp_tx_start_time;
+-struct timeval tp_tx_stop_time;
++ktime_t tp_tx_start_time;
++ktime_t tp_tx_stop_time;
++ktime_t tp_rx_start_time;
++ktime_t tp_rx_stop_time;
+ int tp_tx_cnt;
+ int tp_tx_flag;
+ int tp_tx_buf_cnt = TP_TX_BUF_CNT;
+@@ -222,7 +225,6 @@ static int sdiohal_throughput_tx(void)
+ static void sdiohal_throughput_tx_compute_time(void)
+ {
+ 	static signed long long times_count;
+-	struct timespec64 now;
+ 
+ 	if (tp_tx_flag != 1)
+ 		return;
+@@ -230,17 +232,12 @@ static void sdiohal_throughput_tx_compute_time(void)
+ 	/* throughput test */
+ 	tp_tx_cnt++;
+ 	if (tp_tx_cnt % 500 == 0) {
+-		getnstimeofday(&now);
+-		tp_tx_stop_time.tv_sec = now.tv_sec;
+-		tp_tx_stop_time.tv_usec = now.tv_nsec/1000;
+-		times_count = timeval_to_ns(&tp_tx_stop_time) -
+-			timeval_to_ns(&tp_tx_start_time);
++		tp_tx_stop_time = ktime_get();
++		times_count = tp_tx_stop_time - tp_tx_start_time;
+ 		sdiohal_info("tx->times(500c) is %lldns, tx %d, rx %d\n",
+ 			     times_count, tp_tx_cnt, rx_pop_cnt);
+ 		tp_tx_cnt = 0;
+-		getnstimeofday(&now);
+-		tp_tx_start_time.tv_sec = now.tv_sec;
+-		tp_tx_start_time.tv_usec = now.tv_nsec/1000;
++		tp_tx_start_time = ktime_get();
+ 	}
+ 	sdiohal_throughput_tx();
+ }
+@@ -544,14 +541,10 @@ int at_list_tx_pop(int channel, struct mbuf_t *head,
+ }
+ 
+ int tp_rx_cnt;
+-struct timeval tp_rx_start_time;
+-struct timeval tp_rx_stop_time;
+-struct timespec tp_tm_begin;
+ int at_list_rx_pop(int channel, struct mbuf_t *head,
+ 		   struct mbuf_t *tail, int num)
+ {
+-	static signed long long times_count;
+-	struct timespec64 now;
++	ktime_t times_count;
+ 
+ 	sdiohal_debug("%s channel:%d head:%p tail:%p num:%d\n",
+ 		     __func__, channel, head, tail, num);
+@@ -568,19 +561,13 @@ int at_list_rx_pop(int channel, struct mbuf_t *head,
+ 	/* throughput test */
+ 	tp_rx_cnt += num;
+ 	if (tp_rx_cnt / (500*64) == 1) {
+-		getnstimeofday(&now);
+-		tp_rx_stop_time.tv_sec = now.tv_sec;
+-		tp_rx_stop_time.tv_usec = now.tv_nsec/1000;
+-		times_count = timeval_to_ns(&tp_rx_stop_time)
+-			- timeval_to_ns(&tp_rx_start_time);
++		tp_rx_stop_time = ktime_get();
++		times_count = tp_rx_stop_time - tp_rx_start_time;
+ 		sdiohal_info("rx->times(%dc) is %lldns, tx %d, rx %d\n",
+ 			     tp_rx_cnt, times_count, tp_tx_cnt, rx_pop_cnt);
+ 		tp_rx_cnt = 0;
+-		getnstimeofday(&now);
+-		tp_rx_start_time.tv_sec = now.tv_sec;
+-		tp_rx_start_time.tv_usec = now.tv_nsec/1000;
++		tp_rx_start_time = ktime_get();
+ 	}
+-	getnstimeofday(&tp_tm_begin);
+ 
+ 	return 0;
+ }
+@@ -834,7 +821,6 @@ static ssize_t at_cmd_write(struct file *filp,
+ 	long int long_data;
+ 	int ret;
+ 	unsigned char *send_buf = NULL;
+-	struct timespec64 now;
+ 
+ 	if (count > SDIOHAL_WRITE_SIZE) {
+ 		sdiohal_err("%s write size > %d\n",
+@@ -1127,9 +1113,7 @@ static ssize_t at_cmd_write(struct file *filp,
+ 			__func__, tp_tx_buf_cnt, tp_tx_buf_len);
+ 		tp_tx_flag = 1;
+ 		tp_tx_cnt = 0;
+-		getnstimeofday(&now);
+-		tp_tx_start_time.tv_sec = now.tv_sec;
+-		tp_tx_start_time.tv_usec = now.tv_nsec/1000;
++		tp_tx_start_time = ktime_get();
+ 		if ((tp_tx_buf_cnt <= TP_TX_BUF_CNT) &&
+ 			(tp_tx_buf_len <= TP_TX_BUF_LEN)) {
+ 			sprdwcn_bus_chn_deinit(&at_tx_ops);
+diff --git a/drivers/net/wireless/uwe5622/unisocwifi/wl_core.c b/drivers/net/wireless/uwe5622/unisocwifi/wl_core.c
+index ad310450e79..206824604ec 100755
+--- a/drivers/net/wireless/uwe5622/unisocwifi/wl_core.c
++++ b/drivers/net/wireless/uwe5622/unisocwifi/wl_core.c
+@@ -628,12 +628,12 @@ static int sprdwl_probe(struct platform_device *pdev)
+ 		ret = -ENXIO;
+ 		goto err_core_create;
+ 	}
+-	memcpy(priv->wl_ver.kernel_ver, utsname()->release,
+-			strlen(utsname()->release));
+-	memcpy(priv->wl_ver.drv_ver, SPRDWL_DRIVER_VERSION,
+-			strlen(SPRDWL_DRIVER_VERSION));
+-	memcpy(priv->wl_ver.update, SPRDWL_UPDATE, strlen(SPRDWL_UPDATE));
+-	memcpy(priv->wl_ver.reserve, SPRDWL_RESERVE, strlen(SPRDWL_RESERVE));
++	strncpy(priv->wl_ver.kernel_ver, utsname()->release,
++			sizeof(priv->wl_ver.kernel_ver));
++	strncpy(priv->wl_ver.drv_ver, SPRDWL_DRIVER_VERSION,
++			sizeof(priv->wl_ver.drv_ver));
++	strncpy(priv->wl_ver.update, SPRDWL_UPDATE, sizeof(priv->wl_ver.update));
++	strncpy(priv->wl_ver.reserve, SPRDWL_RESERVE, sizeof(priv->wl_ver.reserve));
+ 	wl_info("Spreadtrum WLAN Version:");
+ 	wl_info("Kernel:%s,Driver:%s,update:%s,reserved:%s\n",
+ 			 utsname()->release, SPRDWL_DRIVER_VERSION,

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/wireless-uwe5622-Fix-compilation-with-6.7-kernel.patch

@@ -0,0 +1,33 @@
+From 4cf270a8ac06021e0f6cf30790d089584cb24b67 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Sat, 23 Dec 2023 10:05:30 +0000
+Subject: [PATCH] wireless: uwe5622: Fix compilation with 6.7 kernel
+
+---
+ drivers/net/wireless/uwe5622/unisocwifi/cfg80211.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/net/wireless/uwe5622/unisocwifi/cfg80211.c b/drivers/net/wireless/uwe5622/unisocwifi/cfg80211.c
+index b2f9a877edce..34b2e5e4274d 100644
+--- a/drivers/net/wireless/uwe5622/unisocwifi/cfg80211.c
++++ b/drivers/net/wireless/uwe5622/unisocwifi/cfg80211.c
+@@ -964,9 +964,16 @@ static int sprdwl_cfg80211_start_ap(struct wiphy *wiphy,
+ 
+ static int sprdwl_cfg80211_change_beacon(struct wiphy *wiphy,
+ 					 struct net_device *ndev,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 7, 0))
++					 struct cfg80211_ap_update *info)
++#else
+ 					 struct cfg80211_beacon_data *beacon)
++#endif
+ {
+ 	struct sprdwl_vif *vif = netdev_priv(ndev);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 7, 0))
++	struct cfg80211_beacon_data *beacon = &(info->beacon);
++#endif
+ 
+ 	wl_ndev_log(L_DBG, ndev, "%s\n", __func__);
+ #ifdef DFS_MASTER
+-- 
+2.34.1
+

recipes-extended/linux/linux-mainline/sunxi-kmeta/bsp/uwe5622/wireless-uwe5622-reduce-system-load.patch

@@ -0,0 +1,29 @@
+From 2bf93d6cfe24f56baa12f75a57b71dfc33fe322a Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Tue, 2 Jan 2024 13:23:23 +0000
+Subject: [PATCH] wireless: uwe5622: reduce system load
+
+Based on https://github.com/pyavitz/debian-image-builder/commit/cbed5020641ad2d2a6c2df0a2ce68586da1b1635
+---
+ drivers/net/wireless/uwe5622/unisocwifi/tx_msg.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/uwe5622/unisocwifi/tx_msg.c b/drivers/net/wireless/uwe5622/unisocwifi/tx_msg.c
+index 40d51a7130d9..040193d3115d 100644
+--- a/drivers/net/wireless/uwe5622/unisocwifi/tx_msg.c
++++ b/drivers/net/wireless/uwe5622/unisocwifi/tx_msg.c
+@@ -317,7 +317,10 @@ void sprdwl_dequeue_data_list(struct mbuf_t *head, int num)
+ /* seam for tx_thread */
+ void tx_down(struct sprdwl_tx_msg *tx_msg)
+ {
+-	wait_for_completion(&tx_msg->tx_completed);
++	int ret;
++	do {
++		ret = wait_for_completion_interruptible(&tx_msg->tx_completed);
++	} while (ret == -ERESTARTSYS);
+ }
+ 
+ void tx_up(struct sprdwl_tx_msg *tx_msg)
+-- 
+2.34.1
+

recipes-extended/linux/linux-mainline_5.15.91.bbappend

@@ -0,0 +1,2 @@
+
+require linux-mainline-changes.inc

recipes-extended/linux/linux-mainline_6.1.9.bbappend

@@ -0,0 +1,4 @@
+
+require linux-mainline-changes.inc
+
+KERNEL_FEATURES:append:orange-pi-3lts = " bsp/orange-pi-3lts/orange-pi-3lts-6_1.scc bsp/uwe5622/uwe5622-6_1.scc bsp/orange-pi-3lts/fix-rtc.scc"

recipes-extended/linux/linux-mainline_6.5.11.bbappend

@@ -0,0 +1,5 @@
+
+require linux-mainline-changes.inc
+
+# Board Specific features
+KERNEL_FEATURES:prepend:orange-pi-3lts = " bsp/orange-pi-3lts/orange-pi-3lts-6_5.scc bsp/uwe5622/uwe5622-6_5.scc bsp/orange-pi-3lts/fix-rtc.scc"

recipes-extended/linux/linux-mainline_6.6.28.bbappend

@@ -0,0 +1,9 @@
+
+require linux-mainline-changes.inc
+
+SRC_URI += "https://www.kernel.org/pub/linux/kernel/v${KRELEASE}.x/linux-${PV}.tar.xz \
+           file://sunxi-kmeta;type=kmeta;name=sunxi-kmeta;destsuffix=sunxi-kmeta \
+           "
+
+KERNEL_FEATURES:prepend:orange-pi-3lts = " bsp/orange-pi-3lts/orange-pi-3lts-6_5.scc bsp/uwe5622/uwe5622-6_6.scc bsp/orange-pi-3lts/fix-rtc.scc"
+KERNEL_FEATURES:prepend:orange-pi-zero2 = " bsp/h61x/orangepi-zero2-6_6.scc bsp/uwe5622/uwe5622-6_6.scc "

recipes-extended/linux/linux-sunxi_3.4.bbappend

@@ -0,0 +1,2 @@
+
+include linux-changes.inc